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Fixed Bug #743 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9513 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-05-24 14:14:31 +00:00
parent 7a28c272f8
commit fe8c9f5277
2 changed files with 15 additions and 14 deletions
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28
os/hal/ports/STM32/STM32F4xx/hal_lld.h
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@ -315,11 +315,11 @@
* @name RCC_PLLCFGR register bits definitions * @name RCC_PLLCFGR register bits definitions
* @{ * @{
*/ */
#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ #define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ #define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ #define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ #define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ #define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ #define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
@ -345,14 +345,14 @@
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ #define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ #define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ #define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ #define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ #define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ #define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ #define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ #define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ #define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ #define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ #define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ #define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
@ -392,11 +392,11 @@
#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ #define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ #define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ #define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ #define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ #define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ #define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ #define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
/** /**
* @name RCC_PLLI2SCFGR register bits definitions * @name RCC_PLLI2SCFGR register bits definitions
@ -1286,7 +1286,7 @@
*/ */
#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) #if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
/** /**
* @brief PLL activation flag. * @brief PLLI2S activation flag.
*/ */
#define STM32_ACTIVATE_PLLI2S TRUE #define STM32_ACTIVATE_PLLI2S TRUE
#else #else
@ -1321,7 +1321,7 @@
#endif #endif
/** /**
* @brief PLL activation flag. * @brief PLLSAI activation flag.
*/ */
#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__) #if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
#define STM32_ACTIVATE_PLLSAI TRUE #define STM32_ACTIVATE_PLLSAI TRUE

1
readme.txt
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@ -73,6 +73,7 @@
***************************************************************************** *****************************************************************************
*** 16.1.5 *** *** 16.1.5 ***
- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742). - HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).
- HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx - HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx
lld files (bug #741). lld files (bug #741).