diff --git a/demos/rt/RT-STM32F303-DISCOVERY/keil/ch.uvproj b/demos/rt/RT-STM32F303-DISCOVERY/keil/ch.uvproj
index 02b0a5cd8..38858cfa1 100644
--- a/demos/rt/RT-STM32F303-DISCOVERY/keil/ch.uvproj
+++ b/demos/rt/RT-STM32F303-DISCOVERY/keil/ch.uvproj
@@ -229,7 +229,7 @@
             <NoZi2>0</NoZi2>
             <NoZi3>0</NoZi3>
             <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
+            <NoZi5>1</NoZi5>
             <Ro1Chk>0</Ro1Chk>
             <Ro2Chk>0</Ro2Chk>
             <Ro3Chk>0</Ro3Chk>
@@ -239,7 +239,7 @@
             <Ra2Chk>0</Ra2Chk>
             <Ra3Chk>0</Ra3Chk>
             <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
+            <Im2Chk>1</Im2Chk>
             <OnChipMemories>
               <Ocm1>
                 <Type>0</Type>
@@ -313,8 +313,8 @@
               </OCR_RVCT5>
               <OCR_RVCT6>
                 <Type>0</Type>
-                <StartAddress>0x2000c000</StartAddress>
-                <Size>0x1</Size>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x2000</Size>
               </OCR_RVCT6>
               <OCR_RVCT7>
                 <Type>0</Type>
@@ -333,8 +333,8 @@
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
-                <StartAddress>0x10000000</StartAddress>
-                <Size>0x2000</Size>
+                <StartAddress>0x2000c000</StartAddress>
+                <Size>0x1</Size>
               </OCR_RVCT10>
             </OnChipMemories>
             <RvctStartVector></RvctStartVector>
@@ -355,7 +355,7 @@
             <uSurpInc>0</uSurpInc>
             <VariousControls>
               <MiscControls>--c99</MiscControls>
-              <Define>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_RAM1$$Base</Define>
+              <Define>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base</Define>
               <Undefine></Undefine>
               <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\ext\CMSIS\include;..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\os\rt\include;..\..\..\..\os\hal\osal\rt;..\..\..\..\os\hal\include;..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY;..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\os\hal\ports\STM32\STM32F30x;..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2;..\..\..\..\os\hal\ports\STM32\LLD\RTCv2;..\..\..\..\os\hal\ports\STM32\LLD\SPIv2;..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\os\hal\ports\STM32\LLD\USARTv2;..\..\..\..\os\hal\ports\STM32\LLD\USBv1;..\..\..\..\test</IncludePath>
             </VariousControls>
@@ -373,7 +373,7 @@
               <MiscControls>--cpreproc</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x</IncludePath>
+              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\rt\ports\ARMCMx</IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -478,6 +478,11 @@
               <FileType>5</FileType>
               <FilePath>..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT\chtypes.h</FilePath>
             </File>
+            <File>
+              <FileName>chcoreasm_v7m.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT\chcoreasm_v7m.s</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
new file mode 100644
index 000000000..282ac547d
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
@@ -0,0 +1,108 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * Imports the Cortex-Mx configuration headers.
+ */
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+CONTEXT_OFFSET  EQU     12
+SCB_ICSR        EQU     0xE000ED04
+
+                PRESERVE8
+                THUMB
+                AREA    |.text|, CODE, READONLY
+
+                IMPORT  chThdExit
+                IMPORT  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                IMPORT  dbg_check_unlock
+                IMPORT  dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+                EXPORT _port_switch
+_port_switch    PROC
+                push    {r4, r5, r6, r7, lr}
+                mov     r4, r8
+                mov     r5, r9
+                mov     r6, r10
+                mov     r7, r11
+                push    {r4, r5, r6, r7}
+                mov     r3, sp
+                str     r3, [r1, #CONTEXT_OFFSET]
+                ldr     r3, [r0, #CONTEXT_OFFSET]
+                mov     sp, r3
+                pop     {r4, r5, r6, r7}
+                mov     r8, r4
+                mov     r9, r5
+                mov     r10, r6
+                mov     r11, r7
+                pop     {r4, r5, r6, r7, pc}
+                ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+                EXPORT  _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+                cpsie   i
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+                ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+                EXPORT  _port_switch_from_isr
+                EXPORT  _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+_port_exit_from_isr
+                ldr     r2, =SCB_ICSR
+                movs    r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+                lsls    r3, r3, #21
+                str     r3, [r2, #0]
+                cpsie   i
+#else
+                lsls    r3, r3, #24
+                str     r3, [r2, #0]
+#endif
+waithere        b       waithere
+                ENDP
+
+                END
diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
new file mode 100644
index 000000000..e9404daba
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * Imports the Cortex-Mx configuration headers.
+ */
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+CONTEXT_OFFSET  EQU     12
+SCB_ICSR        EQU     0xE000ED04
+ICSR_PENDSVSET  EQU     0x10000000
+
+                PRESERVE8
+                THUMB
+                AREA    |.text|, CODE, READONLY
+
+                IMPORT  chThdExit
+                IMPORT  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                IMPORT  dbg_check_unlock
+                IMPORT  dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+                EXPORT _port_switch
+_port_switch    PROC
+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+                vpush   {s16-s31}
+#endif
+                str     sp, [r1, #CONTEXT_OFFSET]                          
+                ldr     sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+                vpop    {s16-s31}
+#endif
+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+                ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+                EXPORT  _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+                cpsie   i
+#else
+                movs    r3, #CORTEX_BASEPRI_DISABLED
+                msr     BASEPRI, r3
+#endif
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+                ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+                EXPORT  _port_switch_from_isr
+                EXPORT  _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+_port_exit_from_isr
+#if CORTEX_SIMPLIFIED_PRIORITY
+                mov     r3, #SCB_ICSR :AND: 0xFFFF
+                movt    r3, #SCB_ICSR :SHR: 16
+                mov     r2, #ICSR_PENDSVSET
+                str     r2, [r3, #0]
+                cpsie   i
+waithere        b       waithere
+#else
+                svc     #0
+#endif
+                ENDP
+
+                END