diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3_4.inc b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3_4.inc
index 719af8e87..95f962abb 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3_4.inc
+++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim3_4.inc
@@ -18,7 +18,7 @@
  * @file    TIMv1/stm32_tim3_4.inc
  * @brief   Shared TIM3, TIM4 handler.
  *
- * @addtogroup STM32_TIM3_TIM4_HANDLER
+ * @addtogroup STM32_TIM3_4_HANDLER
  * @{
  */
 
@@ -104,15 +104,15 @@
 static inline void tim3_tim4_irq_init(void) {
 
 #if defined(STM32_TIM3_IS_USED) || defined(STM32_TIM4_IS_USED)
-  nvicEnableVector(STM32_TIM3_TIM4_NUMBER,
-                   STM32_IRQ_TIM3_TIM4_PRIORITY);
+  nvicEnableVector(STM32_TIM3_4_NUMBER,
+                   STM32_IRQ_TIM3_4_PRIORITY);
 #endif
 }
 
 static inline void tim3_tim4_irq_deinit(void) {
 
 #if defined(STM32_TIM3_IS_USED) || defined(STM32_TIM4_IS_USED)
-  nvicDisableVector(STM32_TIM3_TIM4_NUMBER);
+  nvicDisableVector(STM32_TIM3_4_NUMBER);
 #endif
 }
 
@@ -127,7 +127,7 @@ static inline void tim3_tim4_irq_deinit(void) {
  *
  * @isr
  */
-OSAL_IRQ_HANDLER(STM32_TIM3_TIM4_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_TIM3_4_HANDLER) {
 
   OSAL_IRQ_PROLOGUE();
 
diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_isr.h b/os/hal/ports/STM32/STM32G0xx/stm32_isr.h
index 9b55ee73e..3a0714ce9 100644
--- a/os/hal/ports/STM32/STM32G0xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32G0xx/stm32_isr.h
@@ -134,7 +134,7 @@
 #define STM32_TIM1_CC_HANDLER               Vector78
 #define STM32_TIM2_HANDLER                  Vector7C
 #define STM32_TIM3_HANDLER                  Vector80
-#define STM32_TIM3_TIM4_HANDLER             STM32_TIM3_HANDLER
+#define STM32_TIM3_4_HANDLER                STM32_TIM3_HANDLER
 #define STM32_TIM6_HANDLER                  Vector84
 #define STM32_TIM7_HANDLER                  Vector88
 #define STM32_TIM14_HANDLER                 Vector8C
@@ -146,7 +146,7 @@
 #define STM32_TIM1_CC_NUMBER                14
 #define STM32_TIM2_NUMBER                   15
 #define STM32_TIM3_NUMBER                   16
-#define STM32_TIM3_TIM4_NUMBER              STM32_TIM3_NUMBER
+#define STM32_TIM3_4_NUMBER                 STM32_TIM3_NUMBER
 #define STM32_TIM6_NUMBER                   17
 #define STM32_TIM7_NUMBER                   18
 #define STM32_TIM14_NUMBER                  19
diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h
index 5b55dafd1..adfbb5f49 100644
--- a/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32G0xx/stm32_rcc.h
@@ -635,6 +635,29 @@
  */
 #define rccResetTIM3() rccResetAPBR1(RCC_APBRSTR1_TIM3RST)
 
+/**
+ * @brief   Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPBR1(RCC_APBENR1_TIM4EN, lp)
+
+/**
+ * @brief   Disables the TIM4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM4() rccDisableAPBR1(RCC_APBENR1_TIM4EN)
+
+/**
+ * @brief   Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPBR1(RCC_APBRSTR1_TIM4RST)
+
 /**
  * @brief   Enables the TIM6 peripheral clock.
  *
@@ -734,7 +757,7 @@
  *
  * @api
  */
-#define rccEnableTIM16(lp) rccEnableAPB(RCC_APBENR2_TIM16EN, lp)
+#define rccEnableTIM16(lp) rccEnableAPBR2(RCC_APBENR2_TIM16EN, lp)
 
 /**
  * @brief   Disables the TIM16 peripheral clock.
diff --git a/readme.txt b/readme.txt
index aae3f103f..9c9f646f1 100644
--- a/readme.txt
+++ b/readme.txt
@@ -118,6 +118,7 @@
        instead of a simple size.
 - NEW: RT and NIL upgraded to support the enhanced OSLIB.
 - NEW: Memory areas/pointers checker functions added to OSLIB.
+- FIX: Fixed problems related to TIM3, TIM4 and TIM16 on STM32G0.
 - FIX: Fixed uninitialized return message in EX subsystem (bug #1267)
        (backported to 21.11.4).
 - FIX: Fixed unnecessary code in SNOR device drivers (bug #1265)