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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15866 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2022-12-08 15:02:07 +00:00
parent 49cf68e14a
commit ffc86d58d8
12 changed files with 28 additions and 24 deletions
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4
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

6
os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h
View File

@ -1660,8 +1660,10 @@
/**
* @brief PLL1 DIVP field.
*/
#if ((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \
((STM32_PLL1_DIVP_VALUE & 1) == 0)) || defined(__DOXYGEN__)
#if (STM32_PLL1_DIVP_VALUE == 1) || \
((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \
((STM32_PLL1_DIVP_VALUE & 1) == 0)) || \
defined(__DOXYGEN__)
#define STM32_PLL1_DIVP ((STM32_PLL1_DIVP_VALUE - 1U) << RCC_PLL1DIVR_P1_Pos)
#else
#error "invalid STM32_PLL1_DIVP_VALUE value specified"

6
os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h
View File

@ -1725,8 +1725,10 @@
/**
* @brief PLL1 DIVP field.
*/
#if ((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \
((STM32_PLL1_DIVP_VALUE & 1) == 0)) || defined(__DOXYGEN__)
#if (STM32_PLL1_DIVP_VALUE == 1) || \
((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \
((STM32_PLL1_DIVP_VALUE & 1) == 0)) || \
defined(__DOXYGEN__)
#define STM32_PLL1_DIVP ((STM32_PLL1_DIVP_VALUE - 1U) << RCC_PLL1DIVR_P1_Pos)
#else
#error "invalid STM32_PLL1_DIVP_VALUE value specified"

4
testhal/STM32/multi/ADC/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/multi/DAC/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/multi/EFL-MFS/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/multi/PAL/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/multi/TRNG/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testhal/STM32/multi/UART/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testrt/VT_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY

4
testrt/VT_STORM/cfg/stm32wl55jc_nucleo64_v2/mcuconf.h
View File

@ -53,7 +53,7 @@
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -128,7 +128,7 @@
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY