/**
******************************************************************************
* @file stm32mp151dxx_cm4.h
* @author MCD Application Team
* @brief CMSIS stm32mp151dxx_cm4 Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
* © Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32mp151dxx_cm4
* @{
*/
#ifndef __STM32MP151Dxx_CM4_H
#define __STM32MP151Dxx_CM4_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @brief Bit position definition inside a 32 bits registers
*/
#define B(x) \
((uint32_t) 1 << x)
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32MP1XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
{
/****** Cortex-M Processor Exceptions Numbers *******************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ************************************************************************/
WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */
TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */
RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */
RESERVED_4 = 4, /*!< RESERVED interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC1_IRQn = 18, /*!< ADC1 global Interrupts */
RESERVED_19 = 19, /*!< reserved */
RESERVED_20 = 20, /*!< reserved */
RESERVED_21 = 21, /*!< reserved */
RESERVED_22 = 22, /*!< reserved */
EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */
RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */
EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_IRQn = 54, /*!< TIM6 global */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */
ETH1_IRQn = 61, /*!< Ethernet global Interrupt */
ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
RESERVED_63 = 63, /*!< RESERVED interrupt */
EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */
EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */
EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */
EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */
USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */
EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */
EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
RESERVED_79 = 79, /*!< RESERVED interrupt */
HASH1_IRQn = 80, /*!< Hash global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
LTDC_IRQn = 88, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
ADC2_IRQn = 90, /*!< ADC2 global Interrupts */
SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
OTG_IRQn = 98, /*!< USB On The Go global interrupt */
RESERVED_99 = 99, /*!< RESERVED interrupt */
IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */
IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */
DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */
IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */
IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */
RESERVED_105 = 105, /*!< RESERVED interrupt */
HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */
I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */
I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */
RESERVED_109 = 109, /*!< RESERVED interrupt */
DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */
DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */
DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */
DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */
SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */
TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
TIM12_IRQn = 119, /*!< TIM12 global Interrupt */
MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */
MDMA_IRQn = 122, /*!< MDMA global Interrupt */
RESERVED_123 = 123, /*!< RESERVED interrupt */
SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */
DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */
EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */
nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */
nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */
TIM13_IRQn = 130, /*!< TIM13 global interrupt */
TIM14_IRQn = 131, /*!< TIM14 global interrupt */
DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */
RNG1_IRQn = 133, /*!< RNG1 interrupt */
RNG2_IRQn = 134, /*!< RNG2 interrupt */
I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */
I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */
SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */
LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */
RESERVED_143 = 143, /*!< RESERVED interrupt */
MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */
RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */
SAI4_IRQn = 146, /*!< SAI4 global interrupt */
DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */
RESERVED_148 = 148, /*!< RESERVED interrupt */
WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
MAX_IRQ_n
} IRQn_Type;
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
#define SDC /*!< Step Down Converter feature */
/**
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#include "system_stm32mp1xx.h"
#include
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
__IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
__IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
uint32_t RESERVED1; /*!< Reserved, 0x028 */
uint32_t RESERVED2; /*!< Reserved, 0x02C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x044 */
uint32_t RESERVED4; /*!< Reserved, 0x048 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
__IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
__IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
__IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
__IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
__IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
__IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
uint32_t RESERVED10; /*!< Reserved, 0x0CC */
__IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */
uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
__IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
} ADC_Common_TypeDef;
/**
* @brief Consumer Electronics Control
*/
typedef struct
{
__IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */
__IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */
__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */
__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */
__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */
uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
__IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */
}CEC_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */
uint32_t RESERVED2; /*!< Reserved, 0x00C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */
uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
__IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
__IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */
} DAC_TypeDef;
/*
* @brief DDRCTRL block description (DDRCTRL)
*/
typedef struct
{
__IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */
__IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */
uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
__IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */
__IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */
__IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */
__IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */
__IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */
uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
__IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */
__IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */
__IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */
uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
__IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */
uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
__IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */
__IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */
uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
__IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */
uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
__IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */
__IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */
__IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */
__IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */
__IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */
__IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */
__IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */
uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
__IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */
uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
__IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */
__IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */
__IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */
__IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */
__IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */
__IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */
__IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */
__IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */
__IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */
uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
__IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */
__IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */
uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
__IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */
__IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */
__IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */
__IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */
__IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */
__IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */
__IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */
uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */
__IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */
__IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */
__IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */
uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */
__IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */
uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
__IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */
uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */
__IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */
uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
__IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */
__IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */
__IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */
__IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */
__IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */
__IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */
uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
__IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */
__IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */
__IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */
uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
__IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */
__IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */
uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
__IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */
__IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */
uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */
__IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */
uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */
__IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */
uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */
__IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */
uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
__IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */
__IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */
__IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */
__IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */
__IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */
uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
__IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */
__IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */
uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
__IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */
__IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */
uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
__IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */
__IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */
__IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */
__IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */
uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
__IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */
__IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */
__IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */
__IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */
__IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */
uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
__IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */
__IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */
uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
__IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */
__IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */
__IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */
__IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */
__IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */
} DDRCTRL_TypeDef;
/*
* @brief DDRPERFM block description (DDRPERFM)
*/
typedef struct
{
__IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */
__IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */
__IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */
__IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */
__IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */
__IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */
__IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */
__IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */
uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
__IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */
__IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */
__IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */
uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */
__IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */
uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
__IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */
__IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */
__IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */
__IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */
} DDRPERFM_TypeDef;
/*
* @brief DDRPHYC block description (DDRPHYC)
*/
typedef struct
{
__IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */
__IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */
__IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */
__IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */
__IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */
__IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */
__IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */
__IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */
__IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */
__IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */
__IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */
__IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */
__IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */
__IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */
__IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */
__IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */
__IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */
__IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */
__IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */
__IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */
__IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */
__IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */
__IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */
__IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */
uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
__IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */
__IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */
__IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */
__IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */
__IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */
__IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */
uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
__IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */
__IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */
__IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */
__IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */
__IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */
__IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */
uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
__IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */
__IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */
__IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */
__IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */
__IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */
__IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */
uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
__IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */
__IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */
__IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */
__IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */
__IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */
__IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */
uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
__IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */
__IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */
__IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */
__IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */
__IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */
__IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */
} DDRPHYC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
__IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
} DFSDM_Channel_TypeDef;
/**
* @brief DFSDM registers
*/
typedef struct
{
uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
__IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */
__IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */
__IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */
__IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */
} DFSDM_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */
__IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */
__IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */
__IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */
__IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */
__IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */
__IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */
__IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */
__IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */
__IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */
__IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */
}DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */
uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */
__IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */
} DCMI_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
__IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
__IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */
__IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */
uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */
__IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief MDMA Controller
*/
typedef struct
{
__IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */
uint32_t RESERVED1; /*!< Reserved, 0x004 */
// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */
__IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */
// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */
uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */
__IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */
}MDMA_TypeDef;
typedef struct
{
__IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
__IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
__IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
__IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
__IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
__IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
__IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
__IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
uint32_t RESERVED0; /*!< Reserved, 0x68 */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */
__IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */
__IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */
__IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */
__IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */
__IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */
uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */
__IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */
__IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */
__IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */
__IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */
uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */
__IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */
uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */
__IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */
uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */
__IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */
uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */
__IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */
__IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */
__IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */
uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */
__IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */
__IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */
__IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */
uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */
__IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */
__IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */
uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */
__IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */
__IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */
__IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */
__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */
uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */
__IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */
uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */
__IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */
__IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */
uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */
__IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */
__IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */
uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */
__IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */
__IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */
uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */
__IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */
__IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */
__IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */
__IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */
__IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */
__IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */
__IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */
__IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */
uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */
__IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */
__IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */
__IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */
__IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */
__IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */
uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */
__IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */
__IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */
uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */
__IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */
uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */
__IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */
__IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */
uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */
__IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */
uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */
__IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */
__IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */
__IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */
__IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */
uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */
__IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */
__IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */
uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */
__IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */
__IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */
__IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */
__IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */
uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */
__IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */
__IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */
uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */
__IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */
__IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */
__IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */
__IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */
uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */
__IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */
uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */
__IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */
__IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */
__IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */
__IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */
__IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */
__IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */
__IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */
uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */
__IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */
uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */
__IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */
__IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */
uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */
__IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */
uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */
__IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */
__IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */
__IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */
__IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */
__IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */
__IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */
uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */
__IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */
uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */
__IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */
__IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */
__IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */
__IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */
uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */
__IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */
__IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */
__IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */
__IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */
__IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */
uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */
__IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */
uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */
__IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */
uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */
__IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */
__IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */
__IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */
uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */
__IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */
uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */
__IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */
__IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */
__IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */
__IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */
__IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */
__IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */
__IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */
__IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */
uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */
__IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */
__IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */
__IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */
__IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */
__IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */
__IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */
uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */
__IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */
__IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */
__IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */
__IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */
__IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */
uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */
__IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */
__IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */
__IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */
__IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */
uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */
__IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */
__IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */
__IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */
uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */
__IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */
__IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */
__IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */
uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */
__IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */
uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */
__IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */
__IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */
uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */
__IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */
__IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */
__IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */
__IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */
__IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */
__IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */
uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */
__IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */
uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */
__IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */
uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */
__IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */
uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */
__IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */
__IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */
uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */
__IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */
uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */
__IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */
__IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */
uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */
__IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */
uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */
__IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */
uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */
__IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */
uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */
__IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */
uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */
__IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */
uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */
__IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */
uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */
__IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */
uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */
__IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */
uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */
__IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */
} ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
__IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */
__IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */
__IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */
uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
__IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */
__IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */
__IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */
uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */
__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
__IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */
__IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */
__IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */
uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
__IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
__IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */
__IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */
__IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */
__IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */
uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */
__IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */
__IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */
__IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */
__IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */
__IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */
__IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */
__IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */
__IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */
__IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */
__IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */
__IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */
__IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */
}EXTI_TypeDef;
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */
__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */
}EXTI_Core_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
__IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */
__IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */
uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
__IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */
__IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */
__IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */
uint32_t RESERVED1; /*!< Reserved, 0x25C */
__IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */
__IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */
__IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */
__IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */
uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */
__IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */
__IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */
__IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */
__IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */
__IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */
uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
__IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */
__IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
__IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */
__IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */
uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
__IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */
__IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */
__IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */
__IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */
__IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */
__IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */
__IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */
__IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */
__IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */
__IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */
__IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */
} GPIO_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */
__IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */
__IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */
__IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */
__IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */
__IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */
uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
__IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */
uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
__IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */
uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */
__IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */
} SYSCFG_TypeDef;
/**
* @briefVoltage reference buffer
*/
typedef struct
{
__IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */
__IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */
} VREF_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
__IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
__IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */
uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
__IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */
__IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */
} IWDG_TypeDef;
/**
* @brief JPEG Codec
*/
typedef struct
{
__IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
__IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
__IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
__IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
__IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
__IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
__IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
__IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
__IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
__IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
__IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
__IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
__IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
__IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
__IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
__IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
__IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
__IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
__IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
__IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
__IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
__IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
__IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
__IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
__IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
} JPEG_TypeDef;
/**
* @brief LCD
*/
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
__IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
__IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
__IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
__IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
} LCD_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief USBPHYC USB HS PHY Control
*/
typedef struct
{
__IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */
uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */
__IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */
uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/
__IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */
}USBPHYC_GlobalTypeDef;
/**
* @brief USBPHYC USB HS PHY Control PHYx
*/
typedef struct
{
uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */
__IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */
}USBPHYC_InstanceTypeDef;
/**
* @brief TZC TrustZone Address Space Controller for DDR
*/
typedef struct
{
__IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */
__IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */
__IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */
__IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */
uint8_t RESERVED0[0x100 - 0x10];
__IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */
__IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */
__IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */
__IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */
__IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */
__IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */
/* @TODO : TypeDef to be compleated if needed*/
}TZC_TypeDef;
/**
* @brief TZPC TrustZone Protection Controller
*/
typedef struct
{
__IO uint32_t TZMA0_SIZE; /*!*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VERR)
/******************************* TZPC VERSION ********************************/
#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
/******************************* FMC VERSION ********************************/
#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SYSCFG VERSION ********************************/
#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* ETHERNET VERSION ********************************/
#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
/******************************* EXTI VERSION ********************************/
#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* PWR VERSION ********************************/
#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* RCC VERSION ********************************/
#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* HDP VERSION ********************************/
#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* IPCC VERSION ********************************/
#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* HSEM VERSION ********************************/
#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* GPIO VERSION ********************************/
#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DMA VERSION ********************************/
#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DMAMUX VERSION ********************************/
#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* MDMA VERSION ********************************/
#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* TAMP VERSION ********************************/
#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* RTC VERSION ********************************/
#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SDMMC VERSION ********************************/
#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* QUADSPI VERSION ********************************/
#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* CRC VERSION ********************************/
#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* RNG VERSION ********************************/
#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* HASH VERSION ********************************/
#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DCMI VERSION ********************************/
#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* CEC VERSION ********************************/
#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* LPTIM VERSION ********************************/
#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* TIM VERSION ********************************/
#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* IWDG VERSION ********************************/
#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* WWDG VERSION ********************************/
#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DFSDM VERSION ********************************/
#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SAI VERSION ********************************/
#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* MDIOS VERSION ********************************/
#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* I2C VERSION ********************************/
#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* USART VERSION ********************************/
#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SPDIFRX VERSION ********************************/
#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SPI VERSION ********************************/
#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* ADC VERSION ********************************/
#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DLYB VERSION ********************************/
#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DAC VERSION ********************************/
#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* USBPHYC VERSION ********************************/
#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DEVICE VERSION ********************************/
#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos)
#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000)
/******************************* DEVICE ID ************************************/
#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
/**
* @brief Check whether platform is engineering boot mode
* @param None
* @retval TRUE or FALSE
*/
#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2))
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32MP151Dxx_CM4_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/