/** ****************************************************************************** * @file stm32h503xx.h * @author MCD Application Team * @brief CMSIS STM32H503xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #ifndef STM32H503xx_H #define STM32H503xx_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup ST * @{ */ /** @addtogroup STM32H503xx * @{ */ /** @addtogroup Configuration_of_CMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum { /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* =========================================== STM32H503xx Specific Interrupt Numbers ====================================== */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ TAMP_IRQn = 4, /*!< Tamper global interrupt */ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ RCC_IRQn = 9, /*!< RCC non secure global interrupt */ EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ IWDG_IRQn = 35, /*!< IWDG global interrupt */ ADC1_IRQn = 37, /*!< ADC1 global interrupt */ DAC1_IRQn = 38, /*!< DAC1 global interrupt */ FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ TIM2_IRQn = 45, /*!< TIM2 global interrupt */ TIM3_IRQn = 46, /*!< TIM3 global interrupt */ TIM6_IRQn = 49, /*!< TIM6 global interrupt */ TIM7_IRQn = 50, /*!< TIM7 global interrupt */ I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ SPI1_IRQn = 55, /*!< SPI1 global interrupt */ SPI2_IRQn = 56, /*!< SPI2 global interrupt */ SPI3_IRQn = 57, /*!< SPI3 global interrupt */ USART1_IRQn = 58, /*!< USART1 global interrupt */ USART2_IRQn = 59, /*!< USART2 global interrupt */ USART3_IRQn = 60, /*!< USART3 global interrupt */ LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ CRS_IRQn = 75, /*!< CRS global interrupt */ GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ FPU_IRQn = 103, /*!< FPU global interrupt */ ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ DTS_IRQn = 113, /*!< DTS global interrupt */ RNG_IRQn = 114, /*!< RNG global interrupt */ HASH_IRQn = 117, /*!< HASH global interrupt */ I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ COMP1_IRQn = 133, /*!< COMP global interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ #define __CM33_REV 0x0000U /* Core revision r0p1 */ #define __SAUREGION_PRESENT 1U /* SAU regions present */ #define __MPU_PRESENT 1U /* MPU present */ #define __VTOR_PRESENT 1U /* VTOR present */ #define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ /** @} */ /* End of group Configuration_of_CMSIS */ #include /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_peripherals * @{ */ /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ uint32_t RESERVED3[246]; /*!< Reserved, */ __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Improved Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ } I3C_TypeDef; /** * @brief DAC */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ __IO uint32_t RESERVED[1]; __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ } DAC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ } HASH_DIGEST_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { uint32_t RESERVED0; /*!< Reserved Address offset: 0x00 */ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x08 */ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x08 */ } DMA_TypeDef; typedef struct { __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ } DMA_Channel_TypeDef; /** * @brief Asynch Interrupt/Event Controller (EXTI) */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ uint32_t RESERVED3[4]; /*!< Reserved 3, 0x70 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x10-0x14 */ __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ uint32_t RESERVED3; /*!< Reserved3, Address offset: 0x24 */ __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ uint32_t RESERVED4; /*!< Reserved4, Address offset: 0x2C */ __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x34-0x38 */ __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0x40-0x44 */ __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ uint32_t RESERVED7; /*!< Reserved7, Address offset: 0x4C */ __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ uint32_t RESERVED8[2]; /*!< Reserved8, Address offset: 0x58-0x5C */ __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ uint32_t RESERVED9[2]; /*!< Reserved9, Address offset: 0x68-0x6C */ __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ uint32_t RESERVED10[2]; /*!< Reserved10, Address offset: 0x78-0x7C */ __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ uint32_t RESERVED11[2]; /*!< Reserved11, Address offset: 0x88-0x8C */ __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ uint32_t RESERVED12[10]; /*!< Reserved12, Address offset: 0x98-0xBC */ __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ uint32_t RESERVED13[9]; /*!< Reserved13, Address offset: 0xC4-0xE4 */ __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ uint32_t RESERVED14[2]; /*!< Reserved14, Address offset: 0xF0-0xF4 */ __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ uint32_t RESERVED15[45]; /*!< Reserved15, Address offset: 0x10C-0x1BC */ __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ uint32_t RESERVED16[9]; /*!< Reserved16, Address offset: 0x1C4-0x1E4 */ __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ uint32_t RESERVED17[2]; /*!< Reserved17, Address offset: 0x1F0-0x1F4 */ __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ } FLASH_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ } GPIO_TypeDef; /** * @brief Global TrustZone Controller */ typedef struct { uint32_t RESERVED1[8]; /*!< Reserved1, Address offset: 0x00-0x1C */ __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ uint32_t RESERVED3[17]; /*!< Reserved3, Address offset: 0x2C-0x6C */ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ } GTZC_TZSC_TypeDef; typedef struct { uint32_t RESERVED1[128]; /*!< Reserved1, Address offset: 0x000-0x1FC */ __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ } GTZC_MPCBB_TypeDef; /** * @brief Instruction Cache */ typedef struct { __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ } ICACHE_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ } LPTIM_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ } COMPOPT_TypeDef; typedef struct { __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< Comparator configuration register 1 , Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< Comparator configuration register 2 , Address offset: 0x10 */ } COMP_TypeDef; typedef struct { __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ } OPAMP_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */ __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ uint32_t RESERVED6[43];/*!< Reserved, Address offset: 0x54-0xFC */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x100 */ __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ }PWR_TypeDef; /** * @brief SRAMs configuration controller */ typedef struct { __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ }RAMCFG_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x30 */ __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x44 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x6C */ uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ uint32_t RESERVED12; /*!< Reserved, Address offset: 0x94 */ uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ uint32_t RESERVED16; /*!< Reserved, Address offset: 0xBC */ uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ uint32_t RESERVED21; /*!< Reserved, Address offset: 0x110 */ __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; /* * @brief RTC Specific device feature definitions */ #define RTC_BKP_NB 32U #define RTC_TAMP_NB 2U /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ uint32_t RESERVED3[3];/*!< Reserved, Address offset: 0x64 */ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED2[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ } TAMP_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief System configuration, Boot and Security */ typedef struct { uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ __IO uint32_t RESERVED2[2]; /*!< RESERVED2, Address offset: 0x18 - 0x1C */ __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ uint32_t RESERVED4[36]; /*!< RESERVED4, Address offset: 0x34 - 0xC0 */ uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ uint32_t RESERVED10; /*!< RESERVED10, Address offset: 0x148 */ __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ } SBS_TypeDef; /** * @brief Universal Serial Bus Full Speed Dual Role Device */ typedef struct { __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ __IO uint32_t RESERVED0[8]; /*!< Reserved, */ __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint32_t RESERVED1; /*!< Reserved */ __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ } USB_DRD_TypeDef; /** * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table */ typedef struct { __IO uint32_t TXBD; /*!= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_Peripheral_peripheralAddr * @{ */ /* Internal SRAMs size */ #define SRAM1_SIZE (0x4000UL) /*!< SRAM1=16k */ #define SRAM2_SIZE (0x4000UL) /*!< SRAM2=16k */ #define BKPSRAM_SIZE (0x0800UL) /*!< BKPSRAM=2k */ /* Flash, Peripheral and internal SRAMs base addresses - Non secure */ #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 128 KB) non-secure base address */ #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (16 KB) non-secure base address */ #define SRAM2_BASE_NS (0x20004000UL) /*!< SRAM2 (16 KB) non-secure base address */ #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ /* Peripheral memory map - Non secure */ #define APB1PERIPH_BASE_NS PERIPH_BASE_NS #define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) #define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) #define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) #define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) #define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) /*!< APB1 Non secure peripherals */ #define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) #define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) #define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) #define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) #define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) #define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) #define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) #define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) #define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) #define COMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) #define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) #define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) #define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) #define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) #define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) #define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) #define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) #define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) #define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) #define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) #define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) /*!< APB2 Non secure peripherals */ #define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) #define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) #define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) #define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) #define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) /*!< AHB1 Non secure peripherals */ #define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS #define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) #define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) #define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) #define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) #define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) #define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) #define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) #define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) #define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) #define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) #define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) #define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) #define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) #define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) #define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) #define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) #define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) #define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) #define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) #define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) #define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) #define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) #define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) #define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) #define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) #define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) #define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) #define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) /*!< AHB2 Non secure peripherals */ #define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) #define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) #define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) #define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) #define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) /*!< APB3 Non secure peripherals */ #define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) #define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) #define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) #define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) #define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) #define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) /*!< AHB3 Non secure peripherals */ #define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) #define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) #define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) #define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) /* Debug MCU registers base address */ #define DBGMCU_BASE (0x44024000UL) #define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ #define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ /* Internal Flash OTP Area */ #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ /* Flash system Area */ #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ #define FLASH_SYSTEM_SIZE (0x8000U) /*!< 32 Kbytes system Flash */ /*!< USB PMA SIZE */ #define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ /*!< Non Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF8FE6CUL) #define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF8FE74UL) /************ RSSLIB function return constants ********************************/ #define NSSLIB_ERROR (0xF5F5F5F5UL) #define NSSLIB_SUCCESS (0xEAEAEAEAUL) /*!< RSSLIB pointer function structure address definition */ #define NSSLIB_PFUNC_BASE (0xBF8FE6CUL) #define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) /** * @brief Prototype of RSSLIB Jump to HDP level2 Function * @detail This function increments HDP level up to HDP level 2 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief Prototype of RSSLIB Jump to HDP level3 Function * @detail This function increments HDP level up to HDP level 3 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief RSSLib secure callable function pointer structure */ typedef struct { __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_Peripheral_declaration * @{ */ /*!< APB1 Non secure peripherals */ #define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) #define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) #define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) #define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) #define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) #define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) #define OPAMP1_NS ((OPAMP_TypeDef *)OPAMP1_BASE_NS) #define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) #define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) #define COMP1_NS ((COMP_TypeDef *)COMP1_BASE_NS) #define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) #define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) #define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) #define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) #define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) #define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) #define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) #define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) #define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) #define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) /*!< APB2 Non secure peripherals */ #define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) #define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) #define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) #define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) #define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) /*!< AHB1 Non secure peripherals */ #define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) #define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) #define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) #define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) #define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) #define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) #define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) #define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) #define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) #define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) #define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) #define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) #define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) #define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) #define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) #define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) #define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) #define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) #define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) #define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) #define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) #define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) #define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) #define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) #define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) /*!< AHB2 Non secure peripherals */ #define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) #define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) #define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) #define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) #define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) #define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) /*!< APB3 Non secure peripherals */ #define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) #define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) #define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) #define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) #define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) #define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) /*!< AHB3 Non secure peripherals */ #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) #define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /*!< Memory base addresses for Non secure peripherals */ #define FLASH_BASE FLASH_BASE_NS #define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS #define SRAM1_BASE SRAM1_BASE_NS #define SRAM2_BASE SRAM2_BASE_NS #define BKPSRAM_BASE BKPSRAM_BASE_NS #define PERIPH_BASE PERIPH_BASE_NS #define APB1PERIPH_BASE APB1PERIPH_BASE_NS #define APB2PERIPH_BASE APB2PERIPH_BASE_NS #define APB3PERIPH_BASE APB3PERIPH_BASE_NS #define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS #define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS #define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS /*!< Instance aliases and base addresses for Non secure peripherals */ #define RCC RCC_NS #define RCC_BASE RCC_BASE_NS #define DTS DTS_NS #define DTS_BASE DTS_BASE_NS #define FLASH FLASH_NS #define FLASH_R_BASE FLASH_R_BASE_NS #define GPDMA1 GPDMA1_NS #define GPDMA1_BASE GPDMA1_BASE_NS #define GPDMA1_Channel0 GPDMA1_Channel0_NS #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS #define GPDMA1_Channel1 GPDMA1_Channel1_NS #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS #define GPDMA1_Channel2 GPDMA1_Channel2_NS #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS #define GPDMA1_Channel3 GPDMA1_Channel3_NS #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS #define GPDMA1_Channel4 GPDMA1_Channel4_NS #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS #define GPDMA1_Channel5 GPDMA1_Channel5_NS #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS #define GPDMA1_Channel6 GPDMA1_Channel6_NS #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS #define GPDMA1_Channel7 GPDMA1_Channel7_NS #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS #define GPDMA2 GPDMA2_NS #define GPDMA2_BASE GPDMA2_BASE_NS #define GPDMA2_Channel0 GPDMA2_Channel0_NS #define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS #define GPDMA2_Channel1 GPDMA2_Channel1_NS #define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS #define GPDMA2_Channel2 GPDMA2_Channel2_NS #define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS #define GPDMA2_Channel3 GPDMA2_Channel3_NS #define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS #define GPDMA2_Channel4 GPDMA2_Channel4_NS #define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS #define GPDMA2_Channel5 GPDMA2_Channel5_NS #define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS #define GPDMA2_Channel6 GPDMA2_Channel6_NS #define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS #define GPDMA2_Channel7 GPDMA2_Channel7_NS #define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS #define GPIOA GPIOA_NS #define GPIOA_BASE GPIOA_BASE_NS #define GPIOB GPIOB_NS #define GPIOB_BASE GPIOB_BASE_NS #define GPIOC GPIOC_NS #define GPIOC_BASE GPIOC_BASE_NS #define GPIOD GPIOD_NS #define GPIOD_BASE GPIOD_BASE_NS #define GPIOH GPIOH_NS #define GPIOH_BASE GPIOH_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS #define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS #define RAMCFG_SRAM2 RAMCFG_SRAM2_NS #define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS #define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS #define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS #define EXTI EXTI_NS #define EXTI_BASE EXTI_BASE_NS #define ICACHE ICACHE_NS #define ICACHE_BASE ICACHE_BASE_NS #define GTZC_TZSC1 GTZC_TZSC1_NS #define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS #define GTZC_MPCBB1 GTZC_MPCBB1_NS #define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS #define GTZC_MPCBB2 GTZC_MPCBB2_NS #define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS #define RTC RTC_NS #define RTC_BASE RTC_BASE_NS #define TAMP TAMP_NS #define TAMP_BASE TAMP_BASE_NS #define TIM1 TIM1_NS #define TIM1_BASE TIM1_BASE_NS #define TIM2 TIM2_NS #define TIM2_BASE TIM2_BASE_NS #define TIM3 TIM3_NS #define TIM3_BASE TIM3_BASE_NS #define TIM6 TIM6_NS #define TIM6_BASE TIM6_BASE_NS #define TIM7 TIM7_NS #define TIM7_BASE TIM7_BASE_NS #define WWDG WWDG_NS #define WWDG_BASE WWDG_BASE_NS #define IWDG IWDG_NS #define IWDG_BASE IWDG_BASE_NS #define OPAMP1 OPAMP1_NS #define OPAMP1_BASE OPAMP1_BASE_NS #define SPI1 SPI1_NS #define SPI1_BASE SPI1_BASE_NS #define SPI2 SPI2_NS #define SPI2_BASE SPI2_BASE_NS #define SPI3 SPI3_NS #define SPI3_BASE SPI3_BASE_NS #define COMP1 COMP1_NS #define COMP1_BASE COMP1_BASE_NS #define USART1 USART1_NS #define USART1_BASE USART1_BASE_NS #define USART2 USART2_NS #define USART2_BASE USART2_BASE_NS #define USART3 USART3_NS #define USART3_BASE USART3_BASE_NS #define I2C1 I2C1_NS #define I2C1_BASE I2C1_BASE_NS #define I2C2 I2C2_NS #define I2C2_BASE I2C2_BASE_NS #define I3C1 I3C1_NS #define I3C1_BASE I3C1_BASE_NS #define I3C2 I3C2_NS #define I3C2_BASE I3C2_BASE_NS #define CRS CRS_NS #define CRS_BASE CRS_BASE_NS #define FDCAN1 FDCAN1_NS #define FDCAN1_BASE FDCAN1_BASE_NS #define FDCAN_CONFIG FDCAN_CONFIG_NS #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS #define SRAMCAN_BASE SRAMCAN_BASE_NS #define DAC1 DAC1_NS #define DAC1_BASE DAC1_BASE_NS #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS #define LPTIM2 LPTIM2_NS #define LPTIM2_BASE LPTIM2_BASE_NS #define LPUART1 LPUART1_NS #define LPUART1_BASE LPUART1_BASE_NS #define SBS SBS_NS #define SBS_BASE SBS_BASE_NS #define USB_DRD_FS USB_DRD_FS_NS #define USB_DRD_FS_BASE USB_DRD_BASE_NS #define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS #define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS #define CRC CRC_NS #define CRC_BASE CRC_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADC12_COMMON ADC12_COMMON_NS #define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS #define HASH HASH_NS #define HASH_BASE HASH_BASE_NS #define HASH_DIGEST HASH_DIGEST_NS #define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_EXTSEL_Pos (5U) #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ #define ADC_CFGR2_GCOMP_Pos (16U) #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ #define ADC_CFGR2_SWTRIG_Pos (25U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ #define ADC_CFGR2_BULB_Pos (26U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ #define ADC_CFGR2_SMPTRIG_Pos (27U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ #define ADC_CFGR2_LFTRIG_Pos (29U) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_AWDFILT_Pos (12U) #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ #define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSETPOS_Pos (24U) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR1_SATEN_Pos (25U) #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSETPOS_Pos (24U) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ #define ADC_OFR2_SATEN_Pos (25U) #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSETPOS_Pos (24U) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ #define ADC_OFR3_SATEN_Pos (25U) #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSETPOS_Pos (24U) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ #define ADC_OFR4_SATEN_Pos (25U) #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ /******************** Bit definition for ADC_OR register *****************/ #define ADC_OR_OP0_Pos (0U) #define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ #define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ #define ADC_OR_OP1_Pos (1U) #define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ #define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /**********************************************************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /**********************************************************************************************************************/ /********************************** Bit definition for COMP_SR register *****************************************/ #define COMP_SR_C1VAL_Pos (0U) #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk #define COMP_SR_C1IF_Pos (16U) #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ #define COMP_SR_C1IF COMP_SR_C1IF_Msk /********************************** Bit definition for COMP_ICFR register *****************************************/ #define COMP_ICFR_CC1IF_Pos (16U) #define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ #define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk /********************************** Bit definition for COMP_CFGR1 register **************************************/ #define COMP_CFGR1_EN_Pos (0U) #define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ #define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< COMP1 enable bit */ #define COMP_CFGR1_BRGEN_Pos (1U) #define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ #define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ #define COMP_CFGR1_SCALEN_Pos (2U) #define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ #define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ #define COMP_CFGR1_POLARITY_Pos (3U) #define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ #define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */ #define COMP_CFGR1_ITEN_Pos (6U) #define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ #define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ #define COMP_CFGR1_HYST_Pos (8U) #define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ #define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< COMP1 hysteresis selection bits */ #define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ #define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ #define COMP_CFGR1_PWRMODE_Pos (12U) #define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ #define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ #define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ #define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ #define COMP_CFGR1_INMSEL_Pos (16U) #define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ #define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ #define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ #define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ #define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ #define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ #define COMP_CFGR1_INPSEL1_Pos (20U) #define COMP_CFGR1_INPSEL1_Msk (0x1UL << COMP_CFGR1_INPSEL1_Pos) /*!< 0x00100000 */ #define COMP_CFGR1_INPSEL1 COMP_CFGR1_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ #define COMP_CFGR1_INPSEL2_Pos (22U) #define COMP_CFGR1_INPSEL2_Msk (0x1UL << COMP_CFGR1_INPSEL2_Pos) /*!< 0x00400000 */ #define COMP_CFGR1_INPSEL2 COMP_CFGR1_INPSEL2_Msk /*!< COMP1 input plus 2 selection bit */ #define COMP_CFGR1_BLANKING_Pos (24U) #define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ #define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< COMP1 blanking source selection bits */ #define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ #define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ #define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ #define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ #define COMP_CFGR1_LOCK_Pos (31U) #define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< COMP1 Lock Bit */ /********************************* Bit definition for COMP_CFGR2 register *******************************************/ #define COMP_CFGR2_INPSEL0_Pos (4U) #define COMP_CFGR2_INPSEL0_Msk (0x1UL << COMP_CFGR2_INPSEL0_Pos) /*!< 0x00000010 */ #define COMP_CFGR2_INPSEL0 COMP_CFGR2_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ /**********************************************************************************************************************/ /* */ /* Operational Amplifier (OPAMP) */ /* */ /**********************************************************************************************************************/ /********************************** Bit definition for OPAMP_CSR register *****************************************/ #define OPAMP_CSR_OPAMPxEN_Pos (0U) #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ #define OPAMP_CSR_FORCEVP_Pos (1U) #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */ #define OPAMP_CSR_VPSEL_Pos (2U) #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */ #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ #define OPAMP_CSR_VMSEL_Pos (5U) #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ #define OPAMP_CSR_OPAHSM_Pos (8U) #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */ #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< high speed mode */ #define OPAMP_CSR_CALON_Pos (11U) #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ #define OPAMP_CSR_CALSEL_Pos (12U) #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ #define OPAMP_CSR_PGGAIN_Pos (14U) #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Programmable amplifier gain value */ #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ #define OPAMP_CSR_USERTRIM_Pos (18U) #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */ #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ #define OPAMP_CSR_TSTREF_Pos (29U) #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */ #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< calibration reference voltage output */ #define OPAMP_CSR_CALOUT_Pos (30U) #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */ #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Calibration output */ /********************************** Bit definition for OPAMP_OTR register ******************************************/ #define OPAMP_OTR_TRIMOFFSETN_Pos (0U) #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ #define OPAMP_OTR_TRIMOFFSETP_Pos (8U) #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ /********************************** Bit definition for OPAMP_HSOTR register ***************************************/ #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U) #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */ #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS pairs */ #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */ #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS pairs */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE_Pos (0U) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE_Pos (1U) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ #define CRS_CR_ERRIE_Pos (2U) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ #define CRS_CR_ESYNCIE_Pos (3U) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ #define CRS_CR_CEN_Pos (5U) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN_Pos (6U) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ #define CRS_CR_SWSYNC_Pos (7U) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD_Pos (0U) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ #define CRS_CFGR_FELIM_Pos (16U) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ #define CRS_CFGR_SYNCDIV_Pos (24U) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ #define CRS_CFGR_SYNCSRC_Pos (28U) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ #define CRS_CFGR_SYNCPOL_Pos (31U) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF_Pos (0U) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ #define CRS_ISR_SYNCWARNF_Pos (1U) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ #define CRS_ISR_ERRF_Pos (2U) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ #define CRS_ISR_ESYNCF_Pos (3U) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ #define CRS_ISR_SYNCERR_Pos (8U) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ #define CRS_ISR_SYNCMISS_Pos (9U) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ #define CRS_ISR_TRIMOVF_Pos (10U) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ #define CRS_ISR_FEDIR_Pos (15U) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ #define CRS_ISR_FECAP_Pos (16U) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC_Pos (0U) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC_Pos (1U) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ #define CRS_ICR_ERRC_Pos (2U) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ #define CRS_ICR_ESYNCC_Pos (3U) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk #define RNG_CR_CED_Pos (5U) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk #define RNG_CR_ARDIS_Pos (7U) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk #define RNG_CR_RNG_CONFIG3_Pos (8U) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk #define RNG_CR_NISTC_Pos (12U) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk #define RNG_CR_RNG_CONFIG2_Pos (13U) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk #define RNG_CR_CONDRST_Pos (30U) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk #define RNG_CR_CONFIGLOCK_Pos (31U) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ #define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ /******************* Bits definition for FLASH_ACR register *****************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000U) #define FLASH_ACR_LATENCY_1WS (0x00000001U) #define FLASH_ACR_LATENCY_2WS (0x00000002U) #define FLASH_ACR_LATENCY_3WS (0x00000003U) #define FLASH_ACR_LATENCY_4WS (0x00000004U) #define FLASH_ACR_LATENCY_5WS (0x00000005U) #define FLASH_ACR_LATENCY_6WS (0x00000006U) #define FLASH_ACR_LATENCY_7WS (0x00000007U) #define FLASH_ACR_LATENCY_8WS (0x00000008U) #define FLASH_ACR_LATENCY_9WS (0x00000009U) #define FLASH_ACR_LATENCY_10WS (0x0000000AU) #define FLASH_ACR_LATENCY_11WS (0x0000000BU) #define FLASH_ACR_LATENCY_12WS (0x0000000CU) #define FLASH_ACR_LATENCY_13WS (0x0000000DU) #define FLASH_ACR_LATENCY_14WS (0x0000000EU) #define FLASH_ACR_LATENCY_15WS (0x0000000FU) #define FLASH_ACR_WRHIGHFREQ_Pos (4U) #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ #define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ /******************* Bits definition for FLASH_OPSR register ***************/ #define FLASH_OPSR_ADDR_OP_Pos (0U) #define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ #define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ #define FLASH_OPSR_BK_OP_Pos (22U) #define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ #define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ #define FLASH_OPSR_SYSF_OP_Pos (23U) #define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ #define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ #define FLASH_OPSR_OTP_OP_Pos (24U) #define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ #define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ #define FLASH_OPSR_CODE_OP_Pos (29U) #define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ #define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ #define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ #define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ #define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ /******************* Bits definition for FLASH_OPTCR register *******************/ #define FLASH_OPTCR_OPTLOCK_Pos (0U) #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ #define FLASH_OPTCR_OPTSTART_Pos (1U) #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ #define FLASH_OPTCR_SWAP_BANK_Pos (31U) #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ /******************* Bits definition for FLASH_SR register ***********************/ #define FLASH_SR_BSY_Pos (0U) #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ #define FLASH_SR_WBNE_Pos (1U) #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ #define FLASH_SR_DBNE_Pos (3U) #define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ #define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ #define FLASH_SR_EOP_Pos (16U) #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ #define FLASH_SR_WRPERR_Pos (17U) #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ #define FLASH_SR_PGSERR_Pos (18U) #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ #define FLASH_SR_STRBERR_Pos (19U) #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ #define FLASH_SR_INCERR_Pos (20U) #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ #define FLASH_SR_OPTCHANGEERR_Pos (23U) #define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ #define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ #define FLASH_CR_PG_Pos (1U) #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ #define FLASH_CR_SER_Pos (2U) #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ #define FLASH_CR_BER_Pos (3U) #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ #define FLASH_CR_FW_Pos (4U) #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ #define FLASH_CR_START_Pos (5U) #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ #define FLASH_CR_SNB_Pos (6U) #define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ #define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ #define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ #define FLASH_CR_MER_Pos (15U) #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ #define FLASH_CR_EOPIE_Pos (16U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ #define FLASH_CR_WRPERRIE_Pos (17U) #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ #define FLASH_CR_PGSERRIE_Pos (18U) #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ #define FLASH_CR_STRBERRIE_Pos (19U) #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ #define FLASH_CR_INCERRIE_Pos (20U) #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ #define FLASH_CR_OPTCHANGEERRIE_Pos (23U) #define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ #define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ #define FLASH_CR_INV_Pos (29U) #define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ #define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ #define FLASH_CR_BKSEL_Pos (31U) #define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ #define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ /******************* Bits definition for FLASH_CCR register *******************/ #define FLASH_CCR_CLR_EOP_Pos (16U) #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ #define FLASH_CCR_CLR_WRPERR_Pos (17U) #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ #define FLASH_CCR_CLR_PGSERR_Pos (18U) #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ #define FLASH_CCR_CLR_STRBERR_Pos (19U) #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ #define FLASH_CCR_CLR_INCERR_Pos (20U) #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ #define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) #define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ #define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ /****************** Bits definition for FLASH_PRIVCFGR register ***********/ #define FLASH_PRIVCFGR_NSPRIV_Pos (1U) #define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ #define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ /****************** Bits definition for FLASH_HDPEXTR register *****************/ #define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) #define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ #define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ #define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) #define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ #define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ /******************* Bits definition for FLASH_OPTSR register ***************/ #define FLASH_OPTSR_BOR_LEV_Pos (0U) #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ #define FLASH_OPTSR_BORH_EN_Pos (2U) #define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ #define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ #define FLASH_OPTSR_IWDG_SW_Pos (3U) #define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ #define FLASH_OPTSR_WWDG_SW_Pos (4U) #define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ #define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ #define FLASH_OPTSR_NRST_STOP_Pos (6U) #define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ #define FLASH_OPTSR_NRST_STDBY_Pos (7U) #define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ #define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ #define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) #define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ #define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ #define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) #define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ #define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ #define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) #define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ #define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ #define FLASH_OPTSR_IWDG_STOP_Pos (20U) #define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ #define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTSR_IWDG_STDBY_Pos (21U) #define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ #define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ #define FLASH_OPTSR_SWAP_BANK_Pos (31U) #define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ #define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ /******************* Bits definition for FLASH_EPOCHR register ***************/ #define FLASH_EPOCHR_EPOCH_Pos (0U) #define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ #define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ /******************* Bits definition for FLASH_OPTSR2 register ***************/ #define FLASH_OPTSR2_SRAM2_RST_Pos (3U) #define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ #define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) #define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ #define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ #define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) #define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ #define FLASH_OPTSR2_SRAM1_RST_Pos (9U) #define FLASH_OPTSR2_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_RST_Pos) /*!< 0x00000200 */ #define FLASH_OPTSR2_SRAM1_RST FLASH_OPTSR2_SRAM1_RST_Msk /*!< SRAM1 erase upon a system reset */ #define FLASH_OPTSR2_SRAM1_ECC_Pos (10U) #define FLASH_OPTSR2_SRAM1_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM1_ECC_Pos) /*!< 0x00000400 */ #define FLASH_OPTSR2_SRAM1_ECC FLASH_OPTSR2_SRAM1_ECC_Msk /*!< SRAM1 ECC detection and correction disable */ /**************** Bits definition for FLASH_BOOTR register **********************/ #define FLASH_BOOTR_BOOT_LOCK_Pos (0U) #define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ #define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ #define FLASH_BOOTR_BOOTADD_Pos (8U) #define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ #define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ /**************** Bits definition for FLASH_PRIVBBR register *******************/ #define FLASH_PRIVBBR_PRIVBB_Pos (0U) #define FLASH_PRIVBBR_PRIVBB_Msk (0x000000FFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0x000000FF */ #define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ /***************** Bits definition for FLASH_WRPR register *********************/ #define FLASH_WRPR_WRPSG_Pos (0U) #define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ #define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ /***************** Bits definition for FLASH_HDPR register ********************/ #define FLASH_HDPR_HDP_STRT_Pos (0U) #define FLASH_HDPR_HDP_STRT_Msk (0x07UL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x00000007 */ #define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ #define FLASH_HDPR_HDP_END_Pos (16U) #define FLASH_HDPR_HDP_END_Msk (0x07UL << FLASH_HDPR_HDP_END_Pos) /*!< 0x00070000 */ #define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ /******************* Bits definition for FLASH_ECCR register ***************/ #define FLASH_ECCR_ADDR_ECC_Pos (0U) #define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ #define FLASH_ECCR_BK_ECC_Pos (22U) #define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ #define FLASH_ECCR_SYSF_ECC_Pos (23U) #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ #define FLASH_ECCR_OTP_ECC_Pos (24U) #define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ #define FLASH_ECCR_ECCIE_Pos (25U) #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ #define FLASH_ECCR_ECCC_Pos (30U) #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ #define FLASH_ECCR_ECCD_Pos (31U) #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ /******************* Bits definition for FLASH_ECCDR register ***************/ #define FLASH_ECCDR_FAIL_DATA_Pos (0U) #define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ /******************************************************************************/ /* */ /* General Purpose IOs (GPIO) */ /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ #define GPIO_MODER_MODE0_Pos (0U) #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ #define GPIO_MODER_MODE1_Pos (2U) #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ #define GPIO_MODER_MODE2_Pos (4U) #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ #define GPIO_MODER_MODE3_Pos (6U) #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ #define GPIO_MODER_MODE4_Pos (8U) #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ #define GPIO_MODER_MODE5_Pos (10U) #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ #define GPIO_MODER_MODE6_Pos (12U) #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ #define GPIO_MODER_MODE7_Pos (14U) #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ #define GPIO_MODER_MODE8_Pos (16U) #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ #define GPIO_MODER_MODE9_Pos (18U) #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ #define GPIO_MODER_MODE10_Pos (20U) #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ #define GPIO_MODER_MODE11_Pos (22U) #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ #define GPIO_MODER_MODE12_Pos (24U) #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ #define GPIO_MODER_MODE13_Pos (26U) #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ #define GPIO_MODER_MODE14_Pos (28U) #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ #define GPIO_MODER_MODE15_Pos (30U) #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk #define GPIO_OTYPER_OT1_Pos (1U) #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk #define GPIO_OTYPER_OT2_Pos (2U) #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk #define GPIO_OTYPER_OT3_Pos (3U) #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk #define GPIO_OTYPER_OT4_Pos (4U) #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk #define GPIO_OTYPER_OT5_Pos (5U) #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk #define GPIO_OTYPER_OT6_Pos (6U) #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk #define GPIO_OTYPER_OT7_Pos (7U) #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk #define GPIO_OTYPER_OT8_Pos (8U) #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk #define GPIO_OTYPER_OT9_Pos (9U) #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk #define GPIO_OTYPER_OT10_Pos (10U) #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk #define GPIO_OTYPER_OT11_Pos (11U) #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk #define GPIO_OTYPER_OT12_Pos (12U) #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk #define GPIO_OTYPER_OT13_Pos (13U) #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk #define GPIO_OTYPER_OT14_Pos (14U) #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk #define GPIO_OTYPER_OT15_Pos (15U) #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /****************** Bits definition for GPIO_OSPEEDR register ***************/ #define GPIO_OSPEEDR_OSPEED0_Pos (0U) #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ #define GPIO_OSPEEDR_OSPEED1_Pos (2U) #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ #define GPIO_OSPEEDR_OSPEED2_Pos (4U) #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ #define GPIO_OSPEEDR_OSPEED3_Pos (6U) #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ #define GPIO_OSPEEDR_OSPEED4_Pos (8U) #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ #define GPIO_OSPEEDR_OSPEED5_Pos (10U) #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ #define GPIO_OSPEEDR_OSPEED6_Pos (12U) #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ #define GPIO_OSPEEDR_OSPEED7_Pos (14U) #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ #define GPIO_OSPEEDR_OSPEED8_Pos (16U) #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ #define GPIO_OSPEEDR_OSPEED9_Pos (18U) #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ #define GPIO_OSPEEDR_OSPEED10_Pos (20U) #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ #define GPIO_OSPEEDR_OSPEED11_Pos (22U) #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ #define GPIO_OSPEEDR_OSPEED12_Pos (24U) #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ #define GPIO_OSPEEDR_OSPEED13_Pos (26U) #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ #define GPIO_OSPEEDR_OSPEED14_Pos (28U) #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ #define GPIO_OSPEEDR_OSPEED15_Pos (30U) #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_PUPDR register *****************/ #define GPIO_PUPDR_PUPD0_Pos (0U) #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ #define GPIO_PUPDR_PUPD1_Pos (2U) #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ #define GPIO_PUPDR_PUPD2_Pos (4U) #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ #define GPIO_PUPDR_PUPD3_Pos (6U) #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ #define GPIO_PUPDR_PUPD4_Pos (8U) #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ #define GPIO_PUPDR_PUPD5_Pos (10U) #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ #define GPIO_PUPDR_PUPD6_Pos (12U) #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ #define GPIO_PUPDR_PUPD7_Pos (14U) #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ #define GPIO_PUPDR_PUPD8_Pos (16U) #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ #define GPIO_PUPDR_PUPD9_Pos (18U) #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ #define GPIO_PUPDR_PUPD10_Pos (20U) #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ #define GPIO_PUPDR_PUPD11_Pos (22U) #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ #define GPIO_PUPDR_PUPD12_Pos (24U) #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ #define GPIO_PUPDR_PUPD13_Pos (26U) #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ #define GPIO_PUPDR_PUPD14_Pos (28U) #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ #define GPIO_PUPDR_PUPD15_Pos (30U) #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ #define GPIO_IDR_ID0_Pos (0U) #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk #define GPIO_IDR_ID1_Pos (1U) #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk #define GPIO_IDR_ID2_Pos (2U) #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk #define GPIO_IDR_ID3_Pos (3U) #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk #define GPIO_IDR_ID4_Pos (4U) #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk #define GPIO_IDR_ID5_Pos (5U) #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk #define GPIO_IDR_ID6_Pos (6U) #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk #define GPIO_IDR_ID7_Pos (7U) #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk #define GPIO_IDR_ID8_Pos (8U) #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk #define GPIO_IDR_ID9_Pos (9U) #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk #define GPIO_IDR_ID10_Pos (10U) #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk #define GPIO_IDR_ID11_Pos (11U) #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk #define GPIO_IDR_ID12_Pos (12U) #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk #define GPIO_IDR_ID13_Pos (13U) #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk #define GPIO_IDR_ID14_Pos (14U) #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk #define GPIO_IDR_ID15_Pos (15U) #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bits definition for GPIO_ODR register *******************/ #define GPIO_ODR_OD0_Pos (0U) #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk #define GPIO_ODR_OD1_Pos (1U) #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk #define GPIO_ODR_OD2_Pos (2U) #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk #define GPIO_ODR_OD3_Pos (3U) #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk #define GPIO_ODR_OD4_Pos (4U) #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk #define GPIO_ODR_OD5_Pos (5U) #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk #define GPIO_ODR_OD6_Pos (6U) #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk #define GPIO_ODR_OD7_Pos (7U) #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk #define GPIO_ODR_OD8_Pos (8U) #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk #define GPIO_ODR_OD9_Pos (9U) #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk #define GPIO_ODR_OD10_Pos (10U) #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk #define GPIO_ODR_OD11_Pos (11U) #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk #define GPIO_ODR_OD12_Pos (12U) #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk #define GPIO_ODR_OD13_Pos (13U) #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk #define GPIO_ODR_OD14_Pos (14U) #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk #define GPIO_ODR_OD15_Pos (15U) #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk #define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk #define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk #define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk #define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk #define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk #define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk #define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk #define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk #define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk #define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk #define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk #define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk #define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk #define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk #define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk #define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk #define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk #define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk #define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk #define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk #define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk #define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk #define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk #define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk #define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk #define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk #define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk #define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk #define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk #define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk #define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /****************** Bit definition for GPIO_LCKR register *********************/ #define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk #define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk #define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk #define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk #define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk #define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk #define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk #define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk #define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk #define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk #define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk #define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk #define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk #define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk #define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk #define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk #define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ #define GPIO_AFRL_AFSEL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ #define GPIO_AFRL_AFSEL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ #define GPIO_AFRL_AFSEL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ #define GPIO_AFRL_AFSEL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ #define GPIO_AFRL_AFSEL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ #define GPIO_AFRL_AFSEL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ #define GPIO_AFRL_AFSEL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ #define GPIO_AFRL_AFSEL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ #define GPIO_AFRH_AFSEL8_Pos (0U) #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ #define GPIO_AFRH_AFSEL9_Pos (4U) #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ #define GPIO_AFRH_AFSEL10_Pos (8U) #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ #define GPIO_AFRH_AFSEL11_Pos (12U) #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ #define GPIO_AFRH_AFSEL12_Pos (16U) #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ #define GPIO_AFRH_AFSEL13_Pos (20U) #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ #define GPIO_AFRH_AFSEL14_Pos (24U) #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ #define GPIO_AFRH_AFSEL15_Pos (28U) #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /****************** Bits definition for GPIO_HSLVR register ******************/ #define GPIO_HSLVR_HSLV0_Pos (0U) #define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ #define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk #define GPIO_HSLVR_HSLV1_Pos (1U) #define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ #define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk #define GPIO_HSLVR_HSLV2_Pos (2U) #define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ #define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk #define GPIO_HSLVR_HSLV3_Pos (3U) #define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ #define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk #define GPIO_HSLVR_HSLV4_Pos (4U) #define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ #define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk #define GPIO_HSLVR_HSLV5_Pos (5U) #define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ #define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk #define GPIO_HSLVR_HSLV6_Pos (6U) #define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ #define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk #define GPIO_HSLVR_HSLV7_Pos (7U) #define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ #define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk #define GPIO_HSLVR_HSLV8_Pos (8U) #define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ #define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk #define GPIO_HSLVR_HSLV9_Pos (9U) #define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ #define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk #define GPIO_HSLVR_HSLV10_Pos (10U) #define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ #define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk #define GPIO_HSLVR_HSLV11_Pos (11U) #define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ #define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk #define GPIO_HSLVR_HSLV12_Pos (12U) #define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ #define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk #define GPIO_HSLVR_HSLV13_Pos (13U) #define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ #define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk #define GPIO_HSLVR_HSLV14_Pos (14U) #define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ #define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk #define GPIO_HSLVR_HSLV15_Pos (15U) #define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ #define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk /****************** Bits definition for GPIO_SECCFGR register ******************/ #define GPIO_SECCFGR_SEC0_Pos (0U) #define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ #define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk #define GPIO_SECCFGR_SEC1_Pos (1U) #define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ #define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk #define GPIO_SECCFGR_SEC2_Pos (2U) #define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ #define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk #define GPIO_SECCFGR_SEC3_Pos (3U) #define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ #define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk #define GPIO_SECCFGR_SEC4_Pos (4U) #define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ #define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk #define GPIO_SECCFGR_SEC5_Pos (5U) #define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ #define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk #define GPIO_SECCFGR_SEC6_Pos (6U) #define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ #define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk #define GPIO_SECCFGR_SEC7_Pos (7U) #define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ #define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk #define GPIO_SECCFGR_SEC8_Pos (8U) #define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ #define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk #define GPIO_SECCFGR_SEC9_Pos (9U) #define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ #define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk #define GPIO_SECCFGR_SEC10_Pos (10U) #define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ #define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk #define GPIO_SECCFGR_SEC11_Pos (11U) #define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ #define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk #define GPIO_SECCFGR_SEC12_Pos (12U) #define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ #define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk #define GPIO_SECCFGR_SEC13_Pos (13U) #define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ #define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk #define GPIO_SECCFGR_SEC14_Pos (14U) #define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ #define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk #define GPIO_SECCFGR_SEC15_Pos (15U) #define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ #define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk /******************************************************************************/ /* */ /* ICACHE */ /* */ /******************************************************************************/ /****************** Bit definition for ICACHE_CR register *******************/ #define ICACHE_CR_EN_Pos (0U) #define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ #define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ #define ICACHE_CR_CACHEINV_Pos (1U) #define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ #define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ #define ICACHE_CR_WAYSEL_Pos (2U) #define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ #define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ #define ICACHE_CR_HITMEN_Pos (16U) #define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ #define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ #define ICACHE_CR_MISSMEN_Pos (17U) #define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ #define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ #define ICACHE_CR_HITMRST_Pos (18U) #define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ #define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ #define ICACHE_CR_MISSMRST_Pos (19U) #define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ #define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ /****************** Bit definition for ICACHE_SR register *******************/ #define ICACHE_SR_BUSYF_Pos (0U) #define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ #define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ #define ICACHE_SR_BSYENDF_Pos (1U) #define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ #define ICACHE_SR_ERRF_Pos (2U) #define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ #define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ /****************** Bit definition for ICACHE_IER register ******************/ #define ICACHE_IER_BSYENDIE_Pos (1U) #define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ #define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ #define ICACHE_IER_ERRIE_Pos (2U) #define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ #define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ /****************** Bit definition for ICACHE_FCR register ******************/ #define ICACHE_FCR_CBSYENDF_Pos (1U) #define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ #define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ #define ICACHE_FCR_CERRF_Pos (2U) #define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ #define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ /****************** Bit definition for ICACHE_HMONR register ****************/ #define ICACHE_HMONR_HITMON_Pos (0U) #define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ #define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ /****************** Bit definition for ICACHE_MMONR register ****************/ #define ICACHE_MMONR_MISSMON_Pos (0U) #define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ #define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ /******************************************************************************/ /* */ /* Digital Temperature Sensor (DTS) */ /* */ /******************************************************************************/ /****************** Bit definition for DTS_CFGR1 register ******************/ #define DTS_CFGR1_TS1_EN_Pos (0U) #define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */ #define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS Enable */ #define DTS_CFGR1_TS1_START_Pos (4U) #define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */ #define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS */ #define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U) #define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */ #define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */ #define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */ #define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */ #define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */ #define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */ #define DTS_CFGR1_TS1_SMP_TIME_Pos (16U) #define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */ #define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS */ #define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */ #define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */ #define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */ #define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */ #define DTS_CFGR1_REFCLK_SEL_Pos (20U) #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */ #define DTS_CFGR1_Q_MEAS_OPT_Pos (21U) #define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */ #define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */ #define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U) #define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */ #define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/ /****************** Bit definition for DTS_T0VALR1 register ******************/ #define DTS_T0VALR1_TS1_FMT0_Pos (0U) #define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */ #define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS */ #define DTS_T0VALR1_TS1_T0_Pos (16U) #define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */ #define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS */ /****************** Bit definition for DTS_RAMPVALR register ******************/ #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U) #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */ #define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */ /****************** Bit definition for DTS_ITR1 register ******************/ #define DTS_ITR1_TS1_LITTHD_Pos (0U) #define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */ #define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS */ #define DTS_ITR1_TS1_HITTHD_Pos (16U) #define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */ #define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS */ /****************** Bit definition for DTS_DR register ******************/ #define DTS_DR_TS1_MFREQ_Pos (0U) #define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */ #define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS */ /****************** Bit definition for DTS_SR register ******************/ #define DTS_SR_TS1_ITEF_Pos (0U) #define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */ #define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS */ #define DTS_SR_TS1_ITLF_Pos (1U) #define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */ #define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS */ #define DTS_SR_TS1_ITHF_Pos (2U) #define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */ #define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS */ #define DTS_SR_TS1_AITEF_Pos (4U) #define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */ #define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS */ #define DTS_SR_TS1_AITLF_Pos (5U) #define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */ #define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS */ #define DTS_SR_TS1_AITHF_Pos (6U) #define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */ #define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS */ #define DTS_SR_TS1_RDY_Pos (15U) #define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */ #define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS ready flag */ /****************** Bit definition for DTS_ITENR register ******************/ #define DTS_ITENR_TS1_ITEEN_Pos (0U) #define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */ #define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS */ #define DTS_ITENR_TS1_ITLEN_Pos (1U) #define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */ #define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS */ #define DTS_ITENR_TS1_ITHEN_Pos (2U) #define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */ #define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS */ #define DTS_ITENR_TS1_AITEEN_Pos (4U) #define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */ #define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS */ #define DTS_ITENR_TS1_AITLEN_Pos (5U) #define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */ #define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS */ #define DTS_ITENR_TS1_AITHEN_Pos (6U) #define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */ #define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS */ /****************** Bit definition for DTS_ICIFR register ******************/ #define DTS_ICIFR_TS1_CITEF_Pos (0U) #define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */ #define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS */ #define DTS_ICIFR_TS1_CITLF_Pos (1U) #define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */ #define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS */ #define DTS_ICIFR_TS1_CITHF_Pos (2U) #define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */ #define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS */ #define DTS_ICIFR_TS1_CAITEF_Pos (4U) #define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */ #define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS */ #define DTS_ICIFR_TS1_CAITLF_Pos (5U) #define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */ #define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS */ #define DTS_ICIFR_TS1_CAITHF_Pos (6U) #define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */ #define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS */ /******************************************************************************/ /* */ /* TIM */ /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ #define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_SU_Pos (0U) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMAR_ST_Pos (4U) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMAR_MSK1_Pos (7U) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk #define RTC_ALRMAR_MNU_Pos (8U) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMAR_MNT_Pos (12U) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMAR_MSK2_Pos (15U) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk #define RTC_ALRMAR_HU_Pos (16U) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMAR_HT_Pos (20U) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMAR_PM_Pos (22U) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk #define RTC_ALRMAR_MSK3_Pos (23U) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk #define RTC_ALRMAR_DU_Pos (24U) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMAR_DT_Pos (28U) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMAR_WDSEL_Pos (30U) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk #define RTC_ALRMAR_MSK4_Pos (31U) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_SS_Pos (0U) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk #define RTC_ALRMASSR_MASKSS_Pos (24U) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMASSR_SSCLR_Pos (31U) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ #define RTC_ALRMBR_SU_Pos (0U) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMBR_ST_Pos (4U) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMBR_MSK1_Pos (7U) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk #define RTC_ALRMBR_MNU_Pos (8U) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMBR_MNT_Pos (12U) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMBR_MSK2_Pos (15U) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk #define RTC_ALRMBR_HU_Pos (16U) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMBR_HT_Pos (20U) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMBR_PM_Pos (22U) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk #define RTC_ALRMBR_MSK3_Pos (23U) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk #define RTC_ALRMBR_DU_Pos (24U) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMBR_DT_Pos (28U) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMBR_WDSEL_Pos (30U) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk #define RTC_ALRMBR_MSK4_Pos (31U) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ #define RTC_ALRMBSSR_SS_Pos (0U) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk #define RTC_ALRMBSSR_MASKSS_Pos (24U) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMBSSR_SSCLR_Pos (31U) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ #define RTC_SR_ALRAF_Pos (0U) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk #define RTC_SR_ALRBF_Pos (1U) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk #define RTC_SR_WUTF_Pos (2U) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk #define RTC_SR_TSF_Pos (3U) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk #define RTC_SR_TSOVF_Pos (4U) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk #define RTC_SR_SSRUF_Pos (6U) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ #define RTC_MISR_ALRAMF_Pos (0U) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk #define RTC_MISR_ALRBMF_Pos (1U) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk #define RTC_MISR_WUTMF_Pos (2U) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk #define RTC_MISR_TSMF_Pos (3U) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk #define RTC_MISR_TSOVMF_Pos (4U) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk #define RTC_MISR_ITSMF_Pos (5U) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk #define RTC_MISR_SSRUMF_Pos (6U) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ #define RTC_SCR_CALRAF_Pos (0U) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk #define RTC_SCR_CALRBF_Pos (1U) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk #define RTC_SCR_CWUTF_Pos (2U) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk #define RTC_SCR_CTSF_Pos (3U) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk #define RTC_SCR_CTSOVF_Pos (4U) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk #define RTC_SCR_CSSRUF_Pos (6U) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ #define RTC_ALRABINR_SS_Pos (0U) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ #define RTC_ALRBBINR_SS_Pos (0U) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk #define TAMP_CR1_TAMP2E_Pos (1U) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk #define TAMP_CR1_ITAMP2E_Pos (17U) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk #define TAMP_CR1_ITAMP3E_Pos (18U) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk #define TAMP_CR1_ITAMP4E_Pos (19U) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk #define TAMP_CR1_ITAMP6E_Pos (21U) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk #define TAMP_CR1_ITAMP7E_Pos (22U) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk #define TAMP_CR1_ITAMP9E_Pos (24U) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk #define TAMP_CR1_ITAMP11E_Pos (26U) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk #define TAMP_CR1_ITAMP12E_Pos (27U) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk #define TAMP_CR1_ITAMP13E_Pos (28U) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk #define TAMP_CR1_ITAMP15E_Pos (30U) #define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ #define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ #define TAMP_CR2_TAMP1NOERASE_Pos (0U) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk #define TAMP_CR2_TAMP2NOERASE_Pos (1U) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk #define TAMP_CR2_TAMP1MSK_Pos (16U) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk #define TAMP_CR2_TAMP2MSK_Pos (17U) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk #define TAMP_CR2_BKBLOCK_Pos (22U) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk #define TAMP_CR2_BKERASE_Pos (23U) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk #define TAMP_CR2_TAMP1TRG_Pos (24U) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk #define TAMP_CR2_TAMP2TRG_Pos (25U) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ #define TAMP_CR3_ITAMP1NOER_Pos (0U) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk #define TAMP_CR3_ITAMP2NOER_Pos (1U) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk #define TAMP_CR3_ITAMP3NOER_Pos (2U) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk #define TAMP_CR3_ITAMP4NOER_Pos (3U) #define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk #define TAMP_CR3_ITAMP5NOER_Pos (4U) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk #define TAMP_CR3_ITAMP6NOER_Pos (5U) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk #define TAMP_CR3_ITAMP9NOER_Pos (8U) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk #define TAMP_CR3_ITAMP11NOER_Pos (10U) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk #define TAMP_CR3_ITAMP12NOER_Pos (11U) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk #define TAMP_CR3_ITAMP13NOER_Pos (12U) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk #define TAMP_CR3_ITAMP15NOER_Pos (14U) #define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ #define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ #define TAMP_FLTCR_TAMPFREQ_Pos (0U) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ #define TAMP_FLTCR_TAMPFLT_Pos (3U) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ #define TAMP_FLTCR_TAMPPRCH_Pos (5U) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ #define TAMP_FLTCR_TAMPPUDIS_Pos (7U) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ #define TAMP_ATCR1_TAMP1AM_Pos (0U) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk #define TAMP_ATCR1_TAMP2AM_Pos (1U) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk #define TAMP_ATCR1_ATOSEL1_Pos (8U) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR1_ATOSEL2_Pos (10U) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ #define TAMP_ATCR1_ATOSHARE_Pos (30U) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk #define TAMP_ATCR1_FLTEN_Pos (31U) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ #define TAMP_ATSEEDR_SEED_Pos (0U) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ #define TAMP_ATOR_PRNG_Pos (0U) #define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ #define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ #define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ #define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ #define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ #define TAMP_ATOR_SEEDF_Pos (14U) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk #define TAMP_ATOR_INITS_Pos (15U) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ #define TAMP_ATCR2_ATOSEL1_Pos (8U) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ #define TAMP_ATCR2_ATOSEL2_Pos (11U) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ /* Keep SEC acronym name as following devices (STM32H562xx, STM32H563xx, STM32H573xx) with secure acronym to avoid duplicated bits definitions */ #define TAMP_SECCFGR_BKPRWSEC_Pos (0U) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ #define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ #define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ #define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ #define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ #define TAMP_SECCFGR_BKPWSEC_Pos (16U) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ #define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ #define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ #define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ #define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ /******************** Bits definition for TAMP_PRIVCFGR register ************/ #define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk #define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk #define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk #define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ #define TAMP_IER_TAMP1IE_Pos (0U) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk #define TAMP_IER_TAMP2IE_Pos (1U) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk #define TAMP_IER_ITAMP1IE_Pos (16U) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk #define TAMP_IER_ITAMP2IE_Pos (17U) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk #define TAMP_IER_ITAMP3IE_Pos (18U) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk #define TAMP_IER_ITAMP4IE_Pos (19U) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk #define TAMP_IER_ITAMP5IE_Pos (20U) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk #define TAMP_IER_ITAMP6IE_Pos (21U) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk #define TAMP_IER_ITAMP7IE_Pos (22U) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk #define TAMP_IER_ITAMP8IE_Pos (23U) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk #define TAMP_IER_ITAMP9IE_Pos (24U) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk #define TAMP_IER_ITAMP11IE_Pos (26U) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk #define TAMP_IER_ITAMP12IE_Pos (27U) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk #define TAMP_IER_ITAMP13IE_Pos (28U) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk #define TAMP_IER_ITAMP15IE_Pos (30U) #define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ #define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk /******************** Bits definition for TAMP_SR register *****************/ #define TAMP_SR_TAMP1F_Pos (0U) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk #define TAMP_SR_TAMP2F_Pos (1U) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk #define TAMP_SR_ITAMP1F_Pos (16U) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk #define TAMP_SR_ITAMP2F_Pos (17U) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk #define TAMP_SR_ITAMP3F_Pos (18U) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk #define TAMP_SR_ITAMP4F_Pos (19U) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk #define TAMP_SR_ITAMP5F_Pos (20U) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk #define TAMP_SR_ITAMP6F_Pos (21U) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk #define TAMP_SR_ITAMP7F_Pos (22U) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk #define TAMP_SR_ITAMP8F_Pos (23U) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk #define TAMP_SR_ITAMP9F_Pos (24U) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk #define TAMP_SR_ITAMP11F_Pos (26U) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk #define TAMP_SR_ITAMP12F_Pos (27U) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk #define TAMP_SR_ITAMP13F_Pos (28U) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk #define TAMP_SR_ITAMP15F_Pos (30U) #define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ #define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk /******************** Bits definition for TAMP_MISR register ****************/ #define TAMP_MISR_TAMP1MF_Pos (0U) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk #define TAMP_MISR_TAMP2MF_Pos (1U) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk #define TAMP_MISR_ITAMP1MF_Pos (16U) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk #define TAMP_MISR_ITAMP2MF_Pos (17U) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk #define TAMP_MISR_ITAMP3MF_Pos (18U) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk #define TAMP_MISR_ITAMP4MF_Pos (19U) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk #define TAMP_MISR_ITAMP5MF_Pos (20U) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk #define TAMP_MISR_ITAMP6MF_Pos (21U) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk #define TAMP_MISR_ITAMP7MF_Pos (22U) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk #define TAMP_MISR_ITAMP8MF_Pos (23U) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk #define TAMP_MISR_ITAMP9MF_Pos (24U) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk #define TAMP_MISR_ITAMP11MF_Pos (26U) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk #define TAMP_MISR_ITAMP12MF_Pos (27U) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk #define TAMP_MISR_ITAMP13MF_Pos (28U) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk #define TAMP_MISR_ITAMP15MF_Pos (30U) #define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ #define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ #define TAMP_SCR_CTAMP1F_Pos (0U) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk #define TAMP_SCR_CTAMP2F_Pos (1U) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk #define TAMP_SCR_CITAMP1F_Pos (16U) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk #define TAMP_SCR_CITAMP2F_Pos (17U) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk #define TAMP_SCR_CITAMP3F_Pos (18U) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk #define TAMP_SCR_CITAMP4F_Pos (19U) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk #define TAMP_SCR_CITAMP5F_Pos (20U) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk #define TAMP_SCR_CITAMP6F_Pos (21U) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk #define TAMP_SCR_CITAMP7F_Pos (22U) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk #define TAMP_SCR_CITAMP8F_Pos (23U) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk #define TAMP_SCR_CITAMP9F_Pos (24U) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk #define TAMP_SCR_CITAMP11F_Pos (26U) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk #define TAMP_SCR_CITAMP12F_Pos (27U) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk #define TAMP_SCR_CITAMP13F_Pos (28U) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk #define TAMP_SCR_CITAMP15F_Pos (30U) #define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ #define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk /******************** Bits definition for TAMP_COUNT1R register ***************/ #define TAMP_COUNT1R_COUNT_Pos (0U) #define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ #define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk /******************** Bits definition for TAMP_ERCFG register ***************/ #define TAMP_ERCFGR_ERCFG0_Pos (0U) #define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ #define TAMP_BKP0R_Pos (0U) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ #define TAMP_BKP1R_Pos (0U) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ #define TAMP_BKP2R_Pos (0U) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ #define TAMP_BKP3R_Pos (0U) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ #define TAMP_BKP4R_Pos (0U) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ #define TAMP_BKP5R_Pos (0U) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ #define TAMP_BKP6R_Pos (0U) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ #define TAMP_BKP7R_Pos (0U) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ #define TAMP_BKP8R_Pos (0U) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ #define TAMP_BKP9R_Pos (0U) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ #define TAMP_BKP10R_Pos (0U) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ #define TAMP_BKP11R_Pos (0U) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ #define TAMP_BKP12R_Pos (0U) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ #define TAMP_BKP13R_Pos (0U) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ #define TAMP_BKP14R_Pos (0U) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ #define TAMP_BKP15R_Pos (0U) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ #define TAMP_BKP16R_Pos (0U) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ #define TAMP_BKP17R_Pos (0U) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ #define TAMP_BKP18R_Pos (0U) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ #define TAMP_BKP19R_Pos (0U) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ #define TAMP_BKP20R_Pos (0U) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ #define TAMP_BKP21R_Pos (0U) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ #define TAMP_BKP22R_Pos (0U) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ #define TAMP_BKP23R_Pos (0U) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ #define TAMP_BKP24R_Pos (0U) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ #define TAMP_BKP25R_Pos (0U) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ #define TAMP_BKP26R_Pos (0U) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ #define TAMP_BKP27R_Pos (0U) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ #define TAMP_BKP28R_Pos (0U) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ #define TAMP_BKP29R_Pos (0U) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ #define TAMP_BKP30R_Pos (0U) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ #define TAMP_BKP31R_Pos (0U) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk /******************************************************************************/ /* */ /* SBS */ /* */ /******************************************************************************/ /******************** Bit definition for SBS_HDPLCR register *****************/ #define SBS_HDPLCR_INCR_HDPL_Pos (0U) #define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ #define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ /******************** Bit definition for SBS_HDPLSR register *****************/ #define SBS_HDPLSR_HDPL_Pos (0U) #define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ #define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ /******************** Bit definition for SBS_DBGCR register *****************/ #define SBS_DBGCR_AP_UNLOCK_Pos (0U) #define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ #define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ #define SBS_DBGCR_DBG_UNLOCK_Pos (8U) #define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ #define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ #define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) #define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ #define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ /******************** Bit definition for SBS_DBGLCKR register *****************/ #define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) #define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ #define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ /****************** Bit definition for SBS_PMCR register ****************/ #define SBS_PMCR_PB6_FMP_Pos (16U) #define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ #define SBS_PMCR_PB7_FMP_Pos (17U) #define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ #define SBS_PMCR_PB8_FMP_Pos (18U) #define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ /****************** Bit definition for SBS_FPUIMR register ***************/ #define SBS_FPUIMR_FPU_IE_Pos (0U) #define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ #define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ #define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ #define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ #define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ #define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ #define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ #define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ /****************** Bit definition for SBS_MESR register ****************/ #define SBS_MESR_MCLR_Pos (0U) #define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ #define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ #define SBS_MESR_IPMEE_Pos (16U) #define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ #define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ /****************** Bit definition for SBS_CCCSR register ****************/ #define SBS_CCCSR_EN1_Pos (0U) #define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ #define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ #define SBS_CCCSR_CS1_Pos (1U) #define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ #define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ #define SBS_CCCSR_EN2_Pos (2U) #define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ #define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ #define SBS_CCCSR_CS2_Pos (3U) #define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ #define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ #define SBS_CCCSR_RDY1_Pos (8U) #define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ #define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ #define SBS_CCCSR_RDY2_Pos (9U) #define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ #define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ /****************** Bit definition for SBS_CCVALR register ****************/ #define SBS_CCVALR_ANSRC1_Pos (0U) #define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ #define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ #define SBS_CCVALR_APSRC1_Pos (4U) #define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ #define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ #define SBS_CCVALR_ANSRC2_Pos (8U) #define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ #define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ #define SBS_CCVALR_APSRC2_Pos (12U) #define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ #define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ /****************** Bit definition for SBS_CCSWCR register ****************/ #define SBS_CCSWCR_SW_ANSRC1_Pos (0U) #define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ #define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ #define SBS_CCSWCR_SW_APSRC1_Pos (4U) #define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ #define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ #define SBS_CCSWCR_SW_ANSRC2_Pos (8U) #define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ #define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ #define SBS_CCSWCR_SW_APSRC2_Pos (12U) #define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ #define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ /****************** Bit definition for SBS_CFGR2 register ****************/ #define SBS_CFGR2_CLL_Pos (0U) #define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ #define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ #define SBS_CFGR2_SEL_Pos (1U) #define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ #define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ #define SBS_CFGR2_PVDL_Pos (2U) #define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ #define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ #define SBS_CFGR2_ECCL_Pos (3U) #define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ #define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ /****************** Bit definition for SBS_CNSLCKR register **************/ #define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) #define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ #define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ #define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) #define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ /****************** Bit definition for SBS_ECCNMIR register ***************/ #define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) #define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ #define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ /*****************************************************************************/ /* */ /* Global TrustZone Control */ /* */ /*****************************************************************************/ /******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) #define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) #define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) #define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk /******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) #define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk /******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ /******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/ /*************** Bits definition for register x=1 (TZSC1) *************/ #define GTZC_CFGR1_TIM2_Pos (0U) #define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) #define GTZC_CFGR1_TIM3_Pos (1U) #define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) #define GTZC_CFGR1_TIM6_Pos (4U) #define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) #define GTZC_CFGR1_TIM7_Pos (5U) #define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) #define GTZC_CFGR1_WWDG_Pos (9U) #define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) #define GTZC_CFGR1_IWDG_Pos (10U) #define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) #define GTZC_CFGR1_SPI2_Pos (11U) #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) #define GTZC_CFGR1_SPI3_Pos (12U) #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) #define GTZC_CFGR1_USART2_Pos (13U) #define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) #define GTZC_CFGR1_USART3_Pos (14U) #define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) #define GTZC_CFGR1_I2C1_Pos (17U) #define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) #define GTZC_CFGR1_I2C2_Pos (18U) #define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) #define GTZC_CFGR1_I3C1_Pos (19U) #define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) #define GTZC_CFGR1_CRS_Pos (20U) #define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) #define GTZC_CFGR1_DAC1_Pos (25U) #define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) #define GTZC_CFGR1_DTS_Pos (30U) #define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) #define GTZC_CFGR1_LPTIM2_Pos (31U) #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) /*************** Bits definition for register x=2 (TZSC1) *************/ #define GTZC_CFGR2_FDCAN1_Pos (0U) #define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) #define GTZC_CFGR2_OPAMP_Pos (3U) #define GTZC_CFGR2_OPAMP_Msk (0x01UL << GTZC_CFGR2_OPAMP_Pos) #define GTZC_CFGR2_COMP_Pos (4U) #define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) #define GTZC_CFGR2_TIM1_Pos (8U) #define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) #define GTZC_CFGR2_SPI1_Pos (9U) #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) #define GTZC_CFGR2_USART1_Pos (11U) #define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) #define GTZC_CFGR2_USB_Pos (19U) #define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) #define GTZC_CFGR2_LPUART1_Pos (25U) #define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) #define GTZC_CFGR2_LPTIM1_Pos (28U) #define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) /*************** Bits definition for register x=3 (TZSC1) *************/ #define GTZC_CFGR3_I3C2_Pos (2U) #define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) #define GTZC_CFGR3_CRC_Pos (8U) #define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) #define GTZC_CFGR3_ICACHE_REG_Pos (12U) #define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_CFGR3_ADC_Pos (14U) #define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) #define GTZC_CFGR3_HASH_Pos (17U) #define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) #define GTZC_CFGR3_RNG_Pos (18U) #define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) #define GTZC_CFGR3_RAMCFG_Pos (26U) #define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) /*************** Bits definition for register x=4 (TZSC1) *************/ #define GTZC_CFGR4_GPDMA1_Pos (0U) #define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) #define GTZC_CFGR4_GPDMA2_Pos (1U) #define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) #define GTZC_CFGR4_FLASH_Pos (2U) #define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) #define GTZC_CFGR4_FLASH_REG_Pos (3U) #define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_CFGR4_SBS_Pos (6U) #define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) #define GTZC_CFGR4_RTC_Pos (7U) #define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) #define GTZC_CFGR4_TAMP_Pos (8U) #define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) #define GTZC_CFGR4_PWR_Pos (9U) #define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) #define GTZC_CFGR4_RCC_Pos (10U) #define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) #define GTZC_CFGR4_EXTI_Pos (11U) #define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) #define GTZC_CFGR4_TZSC_Pos (16U) #define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) #define GTZC_CFGR4_BKPSRAM_Pos (20U) #define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) #define GTZC_CFGR4_SRAM1_Pos (24U) #define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_CFGR4_SRAM2_Pos (26U) #define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) #define GTZC_CFGR4_MPCBB2_REG_Pos (27U) #define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) /******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_MPCBB_CR register *****************/ #define GTZC_MPCBB_CR_GLOCK_Pos (0U) #define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ #define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) #define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ #define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) #define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ /******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ /* */ /******************************************************************************/ /****************** Bit definition for USART_CR1 register *******************/ #define USART_CR1_UE_Pos (0U) #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ #define USART_CR1_UESM_Pos (1U) #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ #define USART_CR1_RE_Pos (2U) #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ #define USART_CR1_TE_Pos (3U) #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ #define USART_CR1_IDLEIE_Pos (4U) #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ #define USART_CR1_RXNEIE_Pos (5U) #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */ #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */ #define USART_CR1_TCIE_Pos (6U) #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE /*!< TXE and TX FIFO Not Full Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ #define USART_CR1_PS_Pos (9U) #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ #define USART_CR1_PCE_Pos (10U) #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ #define USART_CR1_WAKE_Pos (11U) #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ #define USART_CR1_M_Pos (12U) #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ #define USART_CR1_M0_Pos (12U) #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ #define USART_CR1_MME_Pos (13U) #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ #define USART_CR1_CMIE_Pos (14U) #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ #define USART_CR1_OVER8_Pos (15U) #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ #define USART_CR1_DEDT_Pos (16U) #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ #define USART_CR1_DEAT_Pos (21U) #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ #define USART_CR1_RTOIE_Pos (26U) #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ #define USART_CR1_EOBIE_Pos (27U) #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ #define USART_CR1_M1_Pos (28U) #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ #define USART_CR1_FIFOEN_Pos (29U) #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ #define USART_CR1_TXFEIE_Pos (30U) #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ #define USART_CR1_RXFFIE_Pos (31U) #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ /****************** Bit definition for USART_CR2 register *******************/ #define USART_CR2_SLVEN_Pos (0U) #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ #define USART_CR2_DIS_NSS_Pos (3U) #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */ #define USART_CR2_ADDM7_Pos (4U) #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ #define USART_CR2_LBDL_Pos (5U) #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ #define USART_CR2_LBDIE_Pos (6U) #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ #define USART_CR2_LBCL_Pos (8U) #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ #define USART_CR2_CPHA_Pos (9U) #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ #define USART_CR2_CPOL_Pos (10U) #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ #define USART_CR2_CLKEN_Pos (11U) #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ #define USART_CR2_STOP_Pos (12U) #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ #define USART_CR2_LINEN_Pos (14U) #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ #define USART_CR2_SWAP_Pos (15U) #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ #define USART_CR2_RXINV_Pos (16U) #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ #define USART_CR2_TXINV_Pos (17U) #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ #define USART_CR2_DATAINV_Pos (18U) #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ #define USART_CR2_MSBFIRST_Pos (19U) #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ #define USART_CR2_ABREN_Pos (20U) #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ #define USART_CR2_ABRMODE_Pos (21U) #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ #define USART_CR2_RTOEN_Pos (23U) #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ #define USART_CR2_ADD_Pos (24U) #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ /****************** Bit definition for USART_CR3 register *******************/ #define USART_CR3_EIE_Pos (0U) #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ #define USART_CR3_IREN_Pos (1U) #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ #define USART_CR3_IRLP_Pos (2U) #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ #define USART_CR3_HDSEL_Pos (3U) #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ #define USART_CR3_NACK_Pos (4U) #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ #define USART_CR3_SCEN_Pos (5U) #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ #define USART_CR3_DMAR_Pos (6U) #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ #define USART_CR3_DMAT_Pos (7U) #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ #define USART_CR3_RTSE_Pos (8U) #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ #define USART_CR3_CTSE_Pos (9U) #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ #define USART_CR3_CTSIE_Pos (10U) #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ #define USART_CR3_ONEBIT_Pos (11U) #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ #define USART_CR3_OVRDIS_Pos (12U) #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ #define USART_CR3_DDRE_Pos (13U) #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ #define USART_CR3_DEM_Pos (14U) #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ #define USART_CR3_DEP_Pos (15U) #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ #define USART_CR3_SCARCNT_Pos (17U) #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ #define USART_CR3_WUS_Pos (20U) #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ #define USART_CR3_WUFIE_Pos (22U) #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ #define USART_CR3_TXFTIE_Pos (23U) #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ #define USART_CR3_TCBGTIE_Pos (24U) #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ #define USART_CR3_RXFTCFG_Pos (25U) #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ #define USART_CR3_RXFTIE_Pos (28U) #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ #define USART_CR3_TXFTCFG_Pos (29U) #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ /****************** Bit definition for USART_BRR register *******************/ #define USART_BRR_LPUART_Pos (0U) #define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */ #define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */ #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ /****************** Bit definition for USART_GTPR register ******************/ #define USART_GTPR_PSC_Pos (0U) #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ #define USART_GTPR_GT_Pos (8U) #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ /******************* Bit definition for USART_RTOR register *****************/ #define USART_RTOR_RTO_Pos (0U) #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ #define USART_RTOR_BLEN_Pos (24U) #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ /******************* Bit definition for USART_RQR register ******************/ #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ /******************* Bit definition for USART_ISR register ******************/ #define USART_ISR_PE_Pos (0U) #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ #define USART_ISR_FE_Pos (1U) #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ #define USART_ISR_NE_Pos (2U) #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ #define USART_ISR_ORE_Pos (3U) #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ #define USART_ISR_IDLE_Pos (4U) #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ #define USART_ISR_RXNE_Pos (5U) #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ #define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos #define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */ #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */ #define USART_ISR_TC_Pos (6U) #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ #define USART_ISR_TXE_Pos (7U) #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ #define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos #define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */ #define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */ #define USART_ISR_LBDF_Pos (8U) #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ #define USART_ISR_CTSIF_Pos (9U) #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ #define USART_ISR_CTS_Pos (10U) #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ #define USART_ISR_RTOF_Pos (11U) #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ #define USART_ISR_EOBF_Pos (12U) #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ #define USART_ISR_UDR_Pos (13U) #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */ #define USART_ISR_ABRE_Pos (14U) #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ #define USART_ISR_ABRF_Pos (15U) #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ #define USART_ISR_BUSY_Pos (16U) #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ #define USART_ISR_CMF_Pos (17U) #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ #define USART_ISR_SBKF_Pos (18U) #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ #define USART_ISR_RWU_Pos (19U) #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ #define USART_ISR_WUF_Pos (20U) #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from low power mode Flag */ #define USART_ISR_TEACK_Pos (21U) #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ #define USART_ISR_REACK_Pos (22U) #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ #define USART_ISR_TXFE_Pos (23U) #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */ #define USART_ISR_RXFF_Pos (24U) #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */ #define USART_ISR_TCBGT_Pos (25U) #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */ #define USART_ISR_RXFT_Pos (26U) #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */ #define USART_ISR_TXFT_Pos (27U) #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */ /******************* Bit definition for USART_ICR register ******************/ #define USART_ICR_PECF_Pos (0U) #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ #define USART_ICR_FECF_Pos (1U) #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ #define USART_ICR_NECF_Pos (2U) #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */ #define USART_ICR_ORECF_Pos (3U) #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ #define USART_ICR_IDLECF_Pos (4U) #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ #define USART_ICR_TXFECF_Pos (5U) #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */ #define USART_ICR_TCCF_Pos (6U) #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ #define USART_ICR_TCBGTCF_Pos (7U) #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ #define USART_ICR_LBDCF_Pos (8U) #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ #define USART_ICR_CTSCF_Pos (9U) #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ #define USART_ICR_RTOCF_Pos (11U) #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ #define USART_ICR_EOBCF_Pos (12U) #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ #define USART_ICR_UDRCF_Pos (13U) #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ #define USART_ICR_CMCF_Pos (17U) #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ #define USART_ICR_WUCF_Pos (20U) #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ /******************* Bit definition for USART_RDR register ******************/ #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ /******************* Bit definition for USART_TDR register ******************/ #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ /******************* Bit definition for USART_PRESC register ****************/ #define USART_PRESC_PRESCALER_Pos (0U) #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ /******************* Bit definition for USART_HWCFGR2 register **************/ #define USART_HWCFGR2_CFG1_Pos (0U) #define USART_HWCFGR2_CFG1_Msk (0xFUL << USART_HWCFGR2_CFG1_Pos) /*!< 0x0000000F */ #define USART_HWCFGR2_CFG1 USART_HWCFGR2_CFG1_Msk /*!< CFG1[3:0] bits (USART hardware configuration 1) */ #define USART_HWCFGR2_CFG2_Pos (4U) #define USART_HWCFGR2_CFG2_Msk (0xFUL << USART_HWCFGR2_CFG2_Pos) /*!< 0x000000F0 */ #define USART_HWCFGR2_CFG2 USART_HWCFGR2_CFG2_Msk /*!< CFG2[7:4] bits (USART hardware configuration 2) */ /******************* Bit definition for USART_HWCFGR1 register **************/ #define USART_HWCFGR1_CFG1_Pos (0U) #define USART_HWCFGR1_CFG1_Msk (0xFUL << USART_HWCFGR1_CFG1_Pos) /*!< 0x0000000F */ #define USART_HWCFGR1_CFG1 USART_HWCFGR1_CFG1_Msk /*!< CFG1[3:0] bits (USART hardware configuration 1) */ #define USART_HWCFGR1_CFG2_Pos (4U) #define USART_HWCFGR1_CFG2_Msk (0xFUL << USART_HWCFGR1_CFG2_Pos) /*!< 0x000000F0 */ #define USART_HWCFGR1_CFG2 USART_HWCFGR1_CFG2_Msk /*!< CFG2[7:4] bits (USART hardware configuration 2) */ #define USART_HWCFGR1_CFG3_Pos (8U) #define USART_HWCFGR1_CFG3_Msk (0xFUL << USART_HWCFGR1_CFG3_Pos) /*!< 0x00000F00 */ #define USART_HWCFGR1_CFG3 USART_HWCFGR1_CFG3_Msk /*!< CFG3[11:8] bits (USART hardware configuration 3) */ #define USART_HWCFGR1_CFG4_Pos (12U) #define USART_HWCFGR1_CFG4_Msk (0xFUL << USART_HWCFGR1_CFG4_Pos) /*!< 0x0000F000 */ #define USART_HWCFGR1_CFG4 USART_HWCFGR1_CFG4_Msk /*!< CFG4[15:12] bits (USART hardware configuration 4) */ #define USART_HWCFGR1_CFG5_Pos (16U) #define USART_HWCFGR1_CFG5_Msk (0xFUL << USART_HWCFGR1_CFG5_Pos) /*!< 0x000F0000 */ #define USART_HWCFGR1_CFG5 USART_HWCFGR1_CFG5_Msk /*!< CFG5[19:16] bits (USART hardware configuration 5) */ #define USART_HWCFGR1_CFG6_Pos (20U) #define USART_HWCFGR1_CFG6_Msk (0xFUL << USART_HWCFGR1_CFG6_Pos) /*!< 0x00F00000 */ #define USART_HWCFGR1_CFG6 USART_HWCFGR1_CFG6_Msk /*!< CFG6[23:20] bits (USART hardware configuration 6) */ #define USART_HWCFGR1_CFG7_Pos (24U) #define USART_HWCFGR1_CFG7_Msk (0xFUL << USART_HWCFGR1_CFG7_Pos) /*!< 0x0F000000 */ #define USART_HWCFGR1_CFG7 USART_HWCFGR1_CFG7_Msk /*!< CFG7[27:24] bits (USART hardware configuration 7) */ #define USART_HWCFGR1_CFG8_Pos (28U) #define USART_HWCFGR1_CFG8_Msk (0xFUL << USART_HWCFGR1_CFG8_Pos) /*!< 0xF0000000 */ #define USART_HWCFGR1_CFG8 USART_HWCFGR1_CFG8_Msk /*!< CFG8[31:28] bits (USART hardware configuration 8) */ /******************* Bit definition for USART_VERR register *****************/ #define USART_VERR_MINREV_Pos (0U) #define USART_VERR_MINREV_Msk (0xFUL << USART_VERR_MINREV_Pos) /*!< 0x0000000F */ #define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */ #define USART_VERR_MAJREV_Pos (4U) #define USART_VERR_MAJREV_Msk (0xFUL << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */ /******************* Bit definition for USART_IPIDR register ****************/ #define USART_IPIDR_ID_Pos (0U) #define USART_IPIDR_ID_Msk (0xFFFFFFFFUL << USART_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ #define USART_IPIDR_ID USART_IPIDR_ID_Msk /*!< ID[31:0] bits (Peripheral identifier) */ /******************* Bit definition for USART_SIDR register ****************/ #define USART_SIDR_ID_Pos (0U) #define USART_SIDR_ID_Msk (0xFFFFFFFFUL << USART_SIDR_ID_Pos) /*!< 0xFFFFFFFF */ #define USART_SIDR_ID USART_SIDR_ID_Msk /*!< SID[31:0] bits (Size identification) */ /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ #define I2C_CR1_PE_Pos (0U) #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ #define I2C_CR1_TXIE_Pos (1U) #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ #define I2C_CR1_RXIE_Pos (2U) #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ #define I2C_CR1_ADDRIE_Pos (3U) #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ #define I2C_CR1_NACKIE_Pos (4U) #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ #define I2C_CR1_STOPIE_Pos (5U) #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ #define I2C_CR1_TCIE_Pos (6U) #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ #define I2C_CR1_ERRIE_Pos (7U) #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ #define I2C_CR1_DNF_Pos (8U) #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ #define I2C_CR1_ANFOFF_Pos (12U) #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ #define I2C_CR1_SWRST_Pos (13U) #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ #define I2C_CR1_TXDMAEN_Pos (14U) #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ #define I2C_CR1_RXDMAEN_Pos (15U) #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ #define I2C_CR1_SBC_Pos (16U) #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ #define I2C_CR1_NOSTRETCH_Pos (17U) #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ #define I2C_CR1_WUPEN_Pos (18U) #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ #define I2C_CR1_GCEN_Pos (19U) #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ #define I2C_CR1_SMBHEN_Pos (20U) #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ #define I2C_CR1_SMBDEN_Pos (21U) #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ #define I2C_CR1_ALERTEN_Pos (22U) #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ #define I2C_CR1_PECEN_Pos (23U) #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ #define I2C_CR1_FMP_Pos (24U) #define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ #define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ /****************** Bit definition for I2C_CR2 register ********************/ #define I2C_CR2_SADD_Pos (0U) #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ #define I2C_CR2_RD_WRN_Pos (10U) #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ #define I2C_CR2_ADD10_Pos (11U) #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ #define I2C_CR2_HEAD10R_Pos (12U) #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ #define I2C_CR2_START_Pos (13U) #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ #define I2C_CR2_STOP_Pos (14U) #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ #define I2C_CR2_NACK_Pos (15U) #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ #define I2C_CR2_NBYTES_Pos (16U) #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ #define I2C_CR2_RELOAD_Pos (24U) #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ #define I2C_CR2_AUTOEND_Pos (25U) #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ #define I2C_CR2_PECBYTE_Pos (26U) #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ #define I2C_OAR1_OA1_Pos (0U) #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ #define I2C_OAR1_OA1MODE_Pos (10U) #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ #define I2C_OAR1_OA1EN_Pos (15U) #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ #define I2C_OAR2_OA2_Pos (1U) #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ #define I2C_OAR2_OA2MSK_Pos (8U) #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ #define I2C_OAR2_OA2MASK01_Pos (8U) #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ #define I2C_OAR2_OA2MASK02_Pos (9U) #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ #define I2C_OAR2_OA2MASK03_Pos (8U) #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ #define I2C_OAR2_OA2MASK04_Pos (10U) #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ #define I2C_OAR2_OA2MASK05_Pos (8U) #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ #define I2C_OAR2_OA2MASK06_Pos (9U) #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ #define I2C_OAR2_OA2MASK07_Pos (8U) #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ #define I2C_OAR2_OA2EN_Pos (15U) #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ #define I2C_TIMINGR_SCLL_Pos (0U) #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ #define I2C_TIMINGR_SCLH_Pos (8U) #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ #define I2C_TIMINGR_SDADEL_Pos (16U) #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ #define I2C_TIMINGR_SCLDEL_Pos (20U) #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ #define I2C_TIMINGR_PRESC_Pos (28U) #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ #define I2C_TIMEOUTR_TIDLE_Pos (12U) #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ #define I2C_TIMEOUTR_TEXTEN_Pos (31U) #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ #define I2C_ISR_TXE_Pos (0U) #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ #define I2C_ISR_TXIS_Pos (1U) #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ #define I2C_ISR_RXNE_Pos (2U) #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ #define I2C_ISR_ADDR_Pos (3U) #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ #define I2C_ISR_NACKF_Pos (4U) #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ #define I2C_ISR_STOPF_Pos (5U) #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ #define I2C_ISR_TC_Pos (6U) #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ #define I2C_ISR_TCR_Pos (7U) #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ #define I2C_ISR_BERR_Pos (8U) #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ #define I2C_ISR_ARLO_Pos (9U) #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ #define I2C_ISR_OVR_Pos (10U) #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ #define I2C_ISR_PECERR_Pos (11U) #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ #define I2C_ISR_TIMEOUT_Pos (12U) #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ #define I2C_ISR_ALERT_Pos (13U) #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ #define I2C_ISR_BUSY_Pos (15U) #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ #define I2C_ISR_DIR_Pos (16U) #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ #define I2C_ISR_ADDCODE_Pos (17U) #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ #define I2C_ICR_ADDRCF_Pos (3U) #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ #define I2C_ICR_NACKCF_Pos (4U) #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ #define I2C_ICR_STOPCF_Pos (5U) #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ #define I2C_ICR_BERRCF_Pos (8U) #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ #define I2C_ICR_ARLOCF_Pos (9U) #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ #define I2C_ICR_OVRCF_Pos (10U) #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ #define I2C_ICR_PECCF_Pos (11U) #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ #define I2C_ICR_TIMOUTCF_Pos (12U) #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ #define I2C_ICR_ALERTCF_Pos (13U) #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ #define I2C_PECR_PEC_Pos (0U) #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ #define I2C_RXDR_RXDATA_Pos (0U) #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ #define I2C_TXDR_TXDATA_Pos (0U) #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ /* Improved Inter-integrated Circuit Interface (I3C) */ /* */ /******************************************************************************/ /******************* Bit definition for I3C_CR register *********************/ #define I3C_CR_DCNT_Pos (0U) #define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ #define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ #define I3C_CR_RNW_Pos (16U) #define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ #define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ #define I3C_CR_CCC_Pos (16U) #define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ #define I3C_CR_ADD_Pos (17U) #define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ #define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ #define I3C_CR_MTYPE_Pos (27U) #define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ #define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ #define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ #define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ #define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ #define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ #define I3C_CR_MEND_Pos (31U) #define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ #define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ /******************* Bit definition for I3C_CFGR register *******************/ #define I3C_CFGR_EN_Pos (0U) #define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ #define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ #define I3C_CFGR_CRINIT_Pos (1U) #define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ #define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ #define I3C_CFGR_NOARBH_Pos (2U) #define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ #define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ #define I3C_CFGR_RSTPTRN_Pos (3U) #define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ #define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ #define I3C_CFGR_EXITPTRN_Pos (4U) #define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ #define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ #define I3C_CFGR_HKSDAEN_Pos (5U) #define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ #define I3C_CFGR_HJACK_Pos (7U) #define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ #define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ #define I3C_CFGR_RXDMAEN_Pos (8U) #define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ #define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ #define I3C_CFGR_RXFLUSH_Pos (9U) #define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ #define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ #define I3C_CFGR_RXTHRES_Pos (10U) #define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ #define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ #define I3C_CFGR_TXDMAEN_Pos (12U) #define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ #define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ #define I3C_CFGR_TXFLUSH_Pos (13U) #define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ #define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ #define I3C_CFGR_TXTHRES_Pos (14U) #define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ #define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ #define I3C_CFGR_SDMAEN_Pos (16U) #define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ #define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ #define I3C_CFGR_SFLUSH_Pos (17U) #define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ #define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ #define I3C_CFGR_SMODE_Pos (18U) #define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ #define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ #define I3C_CFGR_TMODE_Pos (19U) #define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ #define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ #define I3C_CFGR_CDMAEN_Pos (20U) #define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ #define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ #define I3C_CFGR_CFLUSH_Pos (21U) #define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ #define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ #define I3C_CFGR_TSFSET_Pos (30U) #define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ #define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ /******************* Bit definition for I3C_RDR register ********************/ #define I3C_RDR_RDB0_Pos (0U) #define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ /****************** Bit definition for I3C_RDWR register ********************/ #define I3C_RDWR_RDBx_Pos (0U) #define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ #define I3C_RDWR_RDB0_Pos (0U) #define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ #define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ #define I3C_RDWR_RDB1_Pos (8U) #define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ #define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ #define I3C_RDWR_RDB2_Pos (16U) #define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ #define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ #define I3C_RDWR_RDB3_Pos (24U) #define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ #define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ /******************* Bit definition for I3C_TDR register ********************/ #define I3C_TDR_TDB0_Pos (0U) #define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ /****************** Bit definition for I3C_TDWR register ********************/ #define I3C_TDWR_TDBx_Pos (0U) #define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ #define I3C_TDWR_TDB0_Pos (0U) #define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ #define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ #define I3C_TDWR_TDB1_Pos (8U) #define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ #define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ #define I3C_TDWR_TDB2_Pos (16U) #define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ #define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ #define I3C_TDWR_TDB3_Pos (24U) #define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ #define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ /******************* Bit definition for I3C_IBIDR register ******************/ #define I3C_IBIDR_IBIDBx_Pos (0U) #define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ #define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ #define I3C_IBIDR_IBIDB0_Pos (0U) #define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ #define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ #define I3C_IBIDR_IBIDB1_Pos (8U) #define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ #define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ #define I3C_IBIDR_IBIDB2_Pos (16U) #define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ #define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ #define I3C_IBIDR_IBIDB3_Pos (24U) #define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ #define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ /****************** Bit definition for I3C_TGTTDR register ******************/ #define I3C_TGTTDR_TGTTDCNT_Pos (0U) #define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ #define I3C_TGTTDR_PRELOAD_Pos (16U) #define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ #define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ /******************* Bit definition for I3C_SR register *********************/ #define I3C_SR_XDCNT_Pos (0U) #define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ #define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ #define I3C_SR_ABT_Pos (17U) #define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ #define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ #define I3C_SR_DIR_Pos (18U) #define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ #define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ #define I3C_SR_MID_Pos (24U) #define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ #define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ /******************* Bit definition for I3C_SER register ********************/ #define I3C_SER_CODERR_Pos (0U) #define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ #define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ #define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ #define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ #define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ #define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ #define I3C_SER_PERR_Pos (4U) #define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ #define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ #define I3C_SER_STALL_Pos (5U) #define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ #define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ #define I3C_SER_DOVR_Pos (6U) #define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ #define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ #define I3C_SER_COVR_Pos (7U) #define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ #define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ #define I3C_SER_ANACK_Pos (8U) #define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ #define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ #define I3C_SER_DNACK_Pos (9U) #define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ #define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ #define I3C_SER_DERR_Pos (10U) #define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ #define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ /******************* Bit definition for I3C_RMR register ********************/ #define I3C_RMR_IBIRDCNT_Pos (0U) #define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ #define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ #define I3C_RMR_RCODE_Pos (8U) #define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ #define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ #define I3C_RMR_RADD_Pos (17U) #define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ #define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ /******************* Bit definition for I3C_EVR register ********************/ #define I3C_EVR_CFEF_Pos (0U) #define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ #define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ #define I3C_EVR_TXFEF_Pos (1U) #define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ #define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ #define I3C_EVR_CFNFF_Pos (2U) #define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ #define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ #define I3C_EVR_SFNEF_Pos (3U) #define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ #define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ #define I3C_EVR_TXFNFF_Pos (4U) #define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ #define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ #define I3C_EVR_RXFNEF_Pos (5U) #define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ #define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ #define I3C_EVR_TXLASTF_Pos (6U) #define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ #define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ #define I3C_EVR_RXLASTF_Pos (7U) #define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ #define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ #define I3C_EVR_FCF_Pos (9U) #define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ #define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ #define I3C_EVR_RXTGTENDF_Pos (10U) #define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ #define I3C_EVR_ERRF_Pos (11U) #define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ #define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ #define I3C_EVR_IBIF_Pos (15U) #define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ #define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ #define I3C_EVR_IBIENDF_Pos (16U) #define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ #define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ #define I3C_EVR_CRF_Pos (17U) #define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ #define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ #define I3C_EVR_CRUPDF_Pos (18U) #define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ #define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ #define I3C_EVR_HJF_Pos (19U) #define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ #define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ #define I3C_EVR_WKPF_Pos (21U) #define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ #define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ #define I3C_EVR_GETF_Pos (22U) #define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ #define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ #define I3C_EVR_STAF_Pos (23U) #define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ #define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ #define I3C_EVR_DAUPDF_Pos (24U) #define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ #define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ #define I3C_EVR_MWLUPDF_Pos (25U) #define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ #define I3C_EVR_MRLUPDF_Pos (26U) #define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ #define I3C_EVR_RSTF_Pos (27U) #define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ #define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ #define I3C_EVR_ASUPDF_Pos (28U) #define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ #define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ #define I3C_EVR_INTUPDF_Pos (29U) #define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ #define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ #define I3C_EVR_DEFF_Pos (30U) #define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ #define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ #define I3C_EVR_GRPF_Pos (31U) #define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ #define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ /******************* Bit definition for I3C_IER register ********************/ #define I3C_IER_CFNFIE_Pos (2U) #define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ #define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ #define I3C_IER_SFNEIE_Pos (3U) #define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ #define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ #define I3C_IER_TXFNFIE_Pos (4U) #define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ #define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ #define I3C_IER_RXFNEIE_Pos (5U) #define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ #define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ #define I3C_IER_FCIE_Pos (9U) #define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ #define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ #define I3C_IER_RXTGTENDIE_Pos (10U) #define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ #define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ #define I3C_IER_ERRIE_Pos (11U) #define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ #define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ #define I3C_IER_IBIIE_Pos (15U) #define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ #define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ #define I3C_IER_IBIENDIE_Pos (16U) #define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ #define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ #define I3C_IER_CRIE_Pos (17U) #define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ #define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ #define I3C_IER_CRUPDIE_Pos (18U) #define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ #define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ #define I3C_IER_HJIE_Pos (19U) #define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ #define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ #define I3C_IER_WKPIE_Pos (21U) #define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ #define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ #define I3C_IER_GETIE_Pos (22U) #define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ #define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ #define I3C_IER_STAIE_Pos (23U) #define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ #define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ #define I3C_IER_DAUPDIE_Pos (24U) #define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ #define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ #define I3C_IER_MWLUPDIE_Pos (25U) #define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ #define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ #define I3C_IER_MRLUPDIE_Pos (26U) #define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ #define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ #define I3C_IER_RSTIE_Pos (27U) #define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ #define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ #define I3C_IER_ASUPDIE_Pos (28U) #define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ #define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ #define I3C_IER_INTUPDIE_Pos (29U) #define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ #define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ #define I3C_IER_DEFIE_Pos (30U) #define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ #define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ #define I3C_IER_GRPIE_Pos (31U) #define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ #define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ /******************* Bit definition for I3C_CEVR register *******************/ #define I3C_CEVR_CFCF_Pos (9U) #define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ #define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ #define I3C_CEVR_CRXTGTENDF_Pos (10U) #define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ #define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ #define I3C_CEVR_CERRF_Pos (11U) #define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ #define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ #define I3C_CEVR_CIBIF_Pos (15U) #define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ #define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ #define I3C_CEVR_CIBIENDF_Pos (16U) #define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ #define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ #define I3C_CEVR_CCRF_Pos (17U) #define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ #define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ #define I3C_CEVR_CCRUPDF_Pos (18U) #define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ #define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ #define I3C_CEVR_CHJF_Pos (19U) #define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ #define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ #define I3C_CEVR_CWKPF_Pos (21U) #define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ #define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ #define I3C_CEVR_CGETF_Pos (22U) #define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ #define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ #define I3C_CEVR_CSTAF_Pos (23U) #define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ #define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ #define I3C_CEVR_CDAUPDF_Pos (24U) #define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ #define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ #define I3C_CEVR_CMWLUPDF_Pos (25U) #define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ #define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ #define I3C_CEVR_CMRLUPDF_Pos (26U) #define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ #define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ #define I3C_CEVR_CRSTF_Pos (27U) #define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ #define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ #define I3C_CEVR_CASUPDF_Pos (28U) #define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ #define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ #define I3C_CEVR_CINTUPDF_Pos (29U) #define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ #define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ #define I3C_CEVR_CDEFF_Pos (30U) #define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ #define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ #define I3C_CEVR_CGRPF_Pos (31U) #define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ #define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ /****************** Bit definition for I3C_DEVR0 register *******************/ #define I3C_DEVR0_DAVAL_Pos (0U) #define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ #define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ #define I3C_DEVR0_DA_Pos (1U) #define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ #define I3C_DEVR0_IBIEN_Pos (16U) #define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ #define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ #define I3C_DEVR0_CREN_Pos (17U) #define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ #define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ #define I3C_DEVR0_HJEN_Pos (19U) #define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ #define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ #define I3C_DEVR0_AS_Pos (20U) #define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ #define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ #define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ #define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ #define I3C_DEVR0_RSTACT_Pos (22U) #define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ #define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ #define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ #define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ #define I3C_DEVR0_RSTVAL_Pos (24U) #define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ #define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ /****************** Bit definition for I3C_DEVRX register *******************/ #define I3C_DEVRX_DA_Pos (1U) #define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ #define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ #define I3C_DEVRX_IBIACK_Pos (16U) #define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ #define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ #define I3C_DEVRX_CRACK_Pos (17U) #define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ #define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ #define I3C_DEVRX_IBIDEN_Pos (18U) #define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ #define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ #define I3C_DEVRX_SUSP_Pos (19U) #define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ #define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ #define I3C_DEVRX_DIS_Pos (31U) #define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ #define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ /****************** Bit definition for I3C_MAXRLR register ******************/ #define I3C_MAXRLR_MRL_Pos (0U) #define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ #define I3C_MAXRLR_IBIP_Pos (16U) #define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ #define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ #define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ #define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ #define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ /****************** Bit definition for I3C_MAXWLR register ******************/ #define I3C_MAXWLR_MWL_Pos (0U) #define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ #define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ /**************** Bit definition for I3C_TIMINGR0 register ******************/ #define I3C_TIMINGR0_SCLL_PP_Pos (0U) #define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ #define I3C_TIMINGR0_SCLH_I3C_Pos (8U) #define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ #define I3C_TIMINGR0_SCLL_OD_Pos (16U) #define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ #define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ #define I3C_TIMINGR0_SCLH_I2C_Pos (24U) #define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ #define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ /**************** Bit definition for I3C_TIMINGR1 register ******************/ #define I3C_TIMINGR1_AVAL_Pos (0U) #define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ #define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ #define I3C_TIMINGR1_ASNCR_Pos (8U) #define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ #define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ #define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ #define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ #define I3C_TIMINGR1_FREE_Pos (16U) #define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ #define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ #define I3C_TIMINGR1_SDA_HD_Pos (28U) #define I3C_TIMINGR1_SDA_HD_Msk (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x00010000 */ #define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ /**************** Bit definition for I3C_TIMINGR2 register ******************/ #define I3C_TIMINGR2_STALLT_Pos (0U) #define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ #define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ #define I3C_TIMINGR2_STALLD_Pos (1U) #define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ #define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ #define I3C_TIMINGR2_STALLC_Pos (2U) #define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ #define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ #define I3C_TIMINGR2_STALLA_Pos (3U) #define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ #define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ #define I3C_TIMINGR2_STALL_Pos (8U) #define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ #define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ /******************* Bit definition for I3C_BCR register ********************/ #define I3C_BCR_BCR_Pos (0U) #define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ #define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ #define I3C_BCR_BCR0_Pos (0U) #define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ #define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ #define I3C_BCR_BCR1_Pos (1U) #define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ #define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ #define I3C_BCR_BCR2_Pos (2U) #define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ #define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ #define I3C_BCR_BCR6_Pos (6U) #define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ #define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ /******************* Bit definition for I3C_DCR register ********************/ #define I3C_DCR_DCR_Pos (0U) #define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ #define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ /***************** Bit definition for I3C_GETCAPR register ******************/ #define I3C_GETCAPR_CAPPEND_Pos (14U) #define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ #define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ /***************** Bit definition for I3C_CRCAPR register *******************/ #define I3C_CRCAPR_CAPDHOFF_Pos (3U) #define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ #define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ #define I3C_CRCAPR_CAPGRP_Pos (9U) #define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ #define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ /**************** Bit definition for I3C_GETMXDSR register ******************/ #define I3C_GETMXDSR_HOFFAS_Pos (0U) #define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ #define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ #define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ #define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ #define I3C_GETMXDSR_FMT_Pos (8U) #define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ #define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ #define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ #define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ #define I3C_GETMXDSR_RDTURN_Pos (16U) #define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ #define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ #define I3C_GETMXDSR_TSCO_Pos (24U) #define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ /****************** Bit definition for I3C_EPIDR register *******************/ #define I3C_EPIDR_MIPIID_Pos (12U) #define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ #define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ #define I3C_EPIDR_IDTSEL_Pos (16U) #define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ #define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ #define I3C_EPIDR_MIPIMID_Pos (17U) #define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ #define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ /******************************************************************************/ /* */ /* Independent WATCHDOG */ /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ #define IWDG_KR_KEY_Pos (0U) #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!