84 lines
3.4 KiB
C
84 lines
3.4 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32L5xx security configuration.
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*/
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#ifndef SECCONF_H
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#define SECCONF_H
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#define STM32L5xx_SECCONF
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#define STM32L552_SECCONF
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#define STM32L562_SECCONF
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/*
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* Security flash settings.
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*/
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#define STM32_FLASH_SECBB1R1 0x00000000
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#define STM32_FLASH_SECBB1R2 0x00000000
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#define STM32_FLASH_SECBB1R3 0x00000000
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#define STM32_FLASH_SECBB1R4 0x00000000
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#define STM32_FLASH_SECBB2R1 0x00000000
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#define STM32_FLASH_SECBB2R2 0x00000000
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#define STM32_FLASH_SECBB2R3 0x00000000
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#define STM32_FLASH_SECBB2R4 0x00000000
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/*
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* Security RAM settings.
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* VCTR: 256b per bit.
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* LCKVTR: 8kB per bit.
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*/
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#define STM32_MPCBB1_CR (GTZC_MPCBB_CR_SRWILADIS_Msk | GTZC_MPCBB_CR_LCK_Msk)
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#define STM32_MPCBB1_LCKVTR1 0x00000000
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#define STM32_MPCBB1_VCTR0 0xFFFFFFFF
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#define STM32_MPCBB1_VCTR1 0xFFFFFFFF
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#define STM32_MPCBB1_VCTR2 0xFFFFFFFF
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#define STM32_MPCBB1_VCTR3 0xFFFFFFFF
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#define STM32_MPCBB1_VCTR4 0x00000000
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#define STM32_MPCBB1_VCTR5 0x00000000
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#define STM32_MPCBB1_VCTR6 0x00000000
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#define STM32_MPCBB1_VCTR7 0x00000000
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#define STM32_MPCBB1_VCTR8 0x00000000
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#define STM32_MPCBB1_VCTR9 0x00000000
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#define STM32_MPCBB1_VCTR10 0x00000000
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#define STM32_MPCBB1_VCTR11 0x00000000
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#define STM32_MPCBB1_VCTR12 0x00000000
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#define STM32_MPCBB1_VCTR13 0x00000000
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#define STM32_MPCBB1_VCTR14 0x00000000
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#define STM32_MPCBB1_VCTR15 0x00000000
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#define STM32_MPCBB1_VCTR16 0x00000000
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#define STM32_MPCBB1_VCTR17 0x00000000
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#define STM32_MPCBB1_VCTR18 0x00000000
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#define STM32_MPCBB1_VCTR19 0x00000000
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#define STM32_MPCBB1_VCTR20 0x00000000
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#define STM32_MPCBB1_VCTR21 0x00000000
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#define STM32_MPCBB1_VCTR22 0x00000000
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#define STM32_MPCBB1_VCTR23 0x00000000
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#define STM32_MPCBB2_CR (GTZC_MPCBB_CR_SRWILADIS_Msk | GTZC_MPCBB_CR_LCK_Msk)
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#define STM32_MPCBB2_LCKVTR1 0x00000000
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#define STM32_MPCBB2_VCTR0 0x00000000
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#define STM32_MPCBB2_VCTR1 0x00000000
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#define STM32_MPCBB2_VCTR2 0x00000000
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#define STM32_MPCBB2_VCTR3 0x00000000
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#define STM32_MPCBB2_VCTR4 0x00000000
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#define STM32_MPCBB2_VCTR5 0x00000000
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#define STM32_MPCBB2_VCTR6 0x00000000
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#define STM32_MPCBB2_VCTR7 0x00000000
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#endif /* SECCONF_H */
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