326 lines
11 KiB
C
326 lines
11 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file IAR/ARMCMx/chcore.h
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* @brief ARM Cortex-Mx port macros and structures.
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*
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* @addtogroup IAR_ARMCMx_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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#include "nvic.h"
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/*===========================================================================*/
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/* Port constants. */
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/*===========================================================================*/
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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/* Cortex model check, only M0 and M3 supported right now.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
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#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4)
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#warning "untested Cortex-M model"
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#else
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#error "unknown or unsupported Cortex-M model"
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#endif
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/*===========================================================================*/
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/* Port statically derived parameters. */
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/*===========================================================================*/
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/**
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* @brief Disabled value for BASEPRI register.
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* @note ARMv7-M architecture only.
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*/
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#define CORTEX_BASEPRI_DISABLED 0
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/*===========================================================================*/
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/* Port macros. */
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/*===========================================================================*/
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY_MASK(n) \
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((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* Port configurable parameters. */
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/*===========================================================================*/
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/**
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* @brief Enables the use of the WFI instruction in the idle thread loop.
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*/
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#ifndef CORTEX_ENABLE_WFI_IDLE
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#define CORTEX_ENABLE_WFI_IDLE FALSE
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#endif
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/**
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* @brief SYSTICK handler priority.
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* @note The default SYSTICK handler priority is calculated as the priority
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* level in the middle of the numeric priorities range.
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*/
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#ifndef CORTEX_PRIORITY_SYSTICK
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#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
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#else
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/* If it is externally redefined then better perform a validity check on it.*/
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#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
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#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
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#endif
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#endif
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/**
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* @brief SVCALL handler priority.
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* @note The default SVCALL handler priority is calculated as
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* @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves
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* the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
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* priority level.
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* @note The SVCALL vector is only used in the ARMv7-M port, it is available
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* to user in the ARMv6-M port.
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*/
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#ifndef CORTEX_PRIORITY_SVCALL
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#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
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#else
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/* If it is externally redefined then better perform a validity check on it.*/
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#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
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#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
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#endif
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#endif
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/**
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* @brief PENDSV handler priority.
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* @note The default PENDSV handler priority is set at the
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* @p CORTEX_MINIMUM_PRIORITY priority level.
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* @note The PENDSV vector is only used in the ARMv7-M legacy port, it is
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* available to user in the ARMv6-M and ARMv7-M ports.
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* @note In the ARMv7-M legacy port this value should be not changed from
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* the minimum priority level.
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*/
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#ifndef CORTEX_PRIORITY_PENDSV
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#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
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#else
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/* If it is externally redefined then better perform a validity check on it.*/
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#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)
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#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV"
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#endif
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#endif
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/**
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* @brief BASEPRI level within kernel lock.
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* @note This value must not mask the SVCALL priority level or the
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* kernel would hard fault.
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* @note ARMv7-M architecture only.
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*/
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#ifndef CORTEX_BASEPRI_KERNEL
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#define CORTEX_BASEPRI_KERNEL \
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
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#endif
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/**
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* @brief Stack alignment enforcement.
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* @note The default value is 64 in order to comply with EABI, reducing
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* the value to 32 can save some RAM space if you don't care about
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* binary compatibility with EABI compiled libraries.
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* @note Allowed values are 32 or 64.
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*/
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#ifndef CORTEX_STACK_ALIGNMENT
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#define CORTEX_STACK_ALIGNMENT 64
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#endif
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/*===========================================================================*/
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/* Port exported info. */
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/*===========================================================================*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM
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#if defined(__DOXYGEN__)
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/**
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* @brief Macro defining the specific ARM architecture.
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* @note This macro is for documentation only, the real name changes
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* depending on the selected architecture, the possible names are:
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* - CH_ARCHITECTURE_ARM_v6M.
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* - CH_ARCHITECTURE_ARM_v7M.
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* .
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*/
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#define CH_ARCHITECTURE_ARM_vxm
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/**
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* @brief Name of the implemented architecture.
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* @note The value is for documentation only, the real value changes
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* depending on the selected architecture, the possible values are:
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* - "ARMv6-M".
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* - "ARMv7-M".
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* - "ARMv7-ME".
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* .
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*/
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#define CH_ARCHITECTURE_NAME "ARMvx-M"
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/**
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* @brief Name of the architecture variant (optional).
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* @note The value is for documentation only, the real value changes
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* depending on the selected architecture, the possible values are:
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* - "Cortex-M0"
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* - "Cortex-M1"
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* - "Cortex-M3"
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* - "Cortex-M4"
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* .
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*/
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#define CH_CORE_VARIANT_NAME "Cortex-Mx"
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#elif CORTEX_MODEL == CORTEX_M4
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#define CH_ARCHITECTURE_ARM_v7M
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#define CH_ARCHITECTURE_NAME "ARMv7-ME"
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#define CH_CORE_VARIANT_NAME "Cortex-M4"
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#elif CORTEX_MODEL == CORTEX_M3
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#define CH_ARCHITECTURE_ARM_v7M
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#define CH_ARCHITECTURE_NAME "ARMv7-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M3"
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#elif CORTEX_MODEL == CORTEX_M1
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#define CH_ARCHITECTURE_ARM_v6M
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#define CH_ARCHITECTURE_NAME "ARMv6-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M1"
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#elif CORTEX_MODEL == CORTEX_M0
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#define CH_ARCHITECTURE_ARM_v6M
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#define CH_ARCHITECTURE_NAME "ARMv6-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M0"
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#endif
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/*===========================================================================*/
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/* Port implementation part (common). */
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/*===========================================================================*/
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/**
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* @brief Stack and memory alignment enforcement.
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*/
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#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__)
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#if defined(__DOXYGEN__)
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/* Dummy declaration, for Doxygen only.*/
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typedef uint64_t stkalign_t;
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#else
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typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
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#endif
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#elif CORTEX_STACK_ALIGNMENT == 32
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typedef uint32_t stkalign_t __attribute__ ((aligned (4)));
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#else
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#error "invalid stack alignment selected"
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#endif
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/**
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* @brief Generic ARM register.
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*/
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typedef void *regarm_t;
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#if defined(__DOXYGEN__)
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note It is implemented to match the Cortex-Mx exception context.
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*/
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struct extctx {
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/* Dummy definition, just for Doxygen.*/
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};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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*/
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struct intctx {
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/* Dummy definition, just for Doxygen.*/
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};
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#endif
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details In this port the structure just holds a pointer to the @p intctx
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* structure representing the stack pointer at context switch time.
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*/
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struct context {
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struct intctx *r13;
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};
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/**
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* @brief Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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/**
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* @brief Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (INT_REQUIRED_STACK))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
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/* Includes the architecture-specific implementation part.*/
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#if defined(CH_ARCHITECTURE_ARM_v6M)
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#include "chcore_v6m.h"
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#elif defined(CH_ARCHITECTURE_ARM_v7M)
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#include "chcore_v7m.h"
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#endif
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#endif /* _CHCORE_H_ */
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/** @} */
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