186 lines
6.8 KiB
C
186 lines
6.8 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32H7xx/hal_lld.h
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* @brief STM32H7xx HAL subsystem low level driver header.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef HAL_LLD_H
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#define HAL_LLD_H
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#include "stm32_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Requires use of SPIv2 driver model.
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*/
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#define HAL_LLD_SELECT_SPI_V2 TRUE
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/**
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* @brief Sub-family identifier
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*/
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#if !defined(STM32H7XX) || defined(__DOXYGEN__)
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#define STM32H7XX
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#endif
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options (common)
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* @{
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*/
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/**
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* @brief Disables the PWR/RCC initialization in the HAL.
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* @note All the clock tree constants are calculated but the initialization
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* is not performed.
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*/
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#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
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#define STM32_NO_INIT FALSE
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#endif
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/**
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* @brief Target code for this HAL configuration.
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* @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4.
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*/
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#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
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#define STM32_TARGET_CORE 1
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#endif
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/**
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* @brief Enables a no-cache RAM area using the MPU.
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*/
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#if !defined(STM32_NOCACHE_ENABLE) || defined(__DOXYGEN__)
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#define STM32_NOCACHE_ENABLE FALSE
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#endif
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/**
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* @brief MPU region to be used for no-cache RAM area.
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*/
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#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__)
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#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
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#endif
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/**
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* @brief Base address to be used for no-cache RAM area.
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*/
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#if !defined(STM32_NOCACHE_RBAR) || defined(__DOXYGEN__)
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#define STM32_NOCACHE_RBAR 0x24000000U
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#endif
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/**
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* @brief Size to be used for no-cache RAM area.
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*/
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#if !defined(STM32_NOCACHE_RASR) || defined(__DOXYGEN__)
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#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Various helpers.*/
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#include "nvic.h"
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#include "cache.h"
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#include "mpu_v7m.h"
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#if (STM32_NOCACHE_RASR != MPU_RASR_SIZE_32) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_8K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_16K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_32K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512K) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_8M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_16M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_32M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512M) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1G) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2G) && \
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(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4G)
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#error "invalid MPU RASR size value"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if defined(STM32H723xx) || defined(STM32H733xx) || \
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defined(STM32H725xx) || defined(STM32H735xx) || \
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defined(STM32H735xx) || defined(STM32H730xx) || \
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defined(__DOXYGEN__)
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#include "hal_lld_type2.h"
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#elif defined(STM32H7A3xx) || defined(STM32H7B3xx) || \
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defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \
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defined(STM32H7B0xx)
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#include "hal_lld_type3.h"
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#else
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#include "hal_lld_type1.h"
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#endif
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/* Various helpers.*/
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#include "stm32_isr.h"
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#include "stm32_mdma.h"
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#include "stm32_dma.h"
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#include "stm32_bdma.h"
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#include "stm32_exti.h"
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#include "stm32_rcc.h"
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#include "stm32_tim.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void stm32_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_LLD_H */
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/** @} */
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