124 lines
4.6 KiB
C
124 lines
4.6 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/hal_lld.c
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* @brief STM32 HAL subsystem low level driver source.
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* @addtogroup STM32_HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#define AIRCR_VECTKEY 0x05FA0000
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/*===========================================================================*/
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/* Low Level Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Low Level Driver local variables. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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*/
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const STM32GPIOConfig pal_default_config =
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{
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
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#if !defined(STM32F10X_LD)
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{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
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#endif
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#if defined(STM32F10X_HD)
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{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
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{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
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#endif
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};
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/*===========================================================================*/
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/* Low Level Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Low Level Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Low Level Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*/
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void hal_lld_init(void) {
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/* Note: PRIGROUP 4:0 (4:4).*/
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SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1;
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NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
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NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
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/* Systick initialization.*/
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SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT;
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#if CH_HAL_USE_ADC || CH_HAL_USE_SPI
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dmaInit();
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#endif
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}
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/**
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* @brief STM32 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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*/
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void stm32_clock_init(void) {
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/* HSI setup.*/
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RCC->CR = 0x00000083; /* Reset value, HSI ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Waits until HSI stable. */
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/* HSE setup.*/
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE stable. */
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/* PLL setup.*/
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RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL stable. */
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/* Clock sources.*/
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
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RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
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RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
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/* Flash setup and final clock selection. */
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FLASH->ACR = FLASHBITS; /* Flash wait states depending on clock. */
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RCC->CFGR |= RCC_CFGR_SW_PLL; /* Switches the PLL clock ON. */
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while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
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;
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}
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/** @} */
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