851 lines
23 KiB
C
851 lines
23 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32WLxx/stm32_rcc.h
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* @brief RCC helper driver header.
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* @note This file requires definitions from the ST header file
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* @p stm32wlxx.h.
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*
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* @addtogroup STM32WLxx_RCC
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* @{
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*/
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#ifndef STM32_RCC_H
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#define STM32_RCC_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Generic RCC operations
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* @{
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*/
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
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*
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* @param[in] mask APB1 R1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1R1(mask, lp) { \
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RCC->APB1ENR1 |= (mask); \
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if (lp) \
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RCC->APB1SMENR1 |= (mask); \
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else \
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RCC->APB1SMENR1 &= ~(mask); \
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(void)RCC->APB1SMENR1; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
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*
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* @param[in] mask APB1 R1 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB1R1(mask) { \
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RCC->APB1ENR1 &= ~(mask); \
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RCC->APB1SMENR1 &= ~(mask); \
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(void)RCC->APB1SMENR1; \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus (R1).
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*
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* @param[in] mask APB1 R1 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB1R1(mask) { \
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RCC->APB1RSTR1 |= (mask); \
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RCC->APB1RSTR1 &= ~(mask); \
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(void)RCC->APB1RSTR1; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
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*
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* @param[in] mask APB1 R2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1R2(mask, lp) { \
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RCC->APB1ENR2 |= (mask); \
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if (lp) \
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RCC->APB1SMENR2 |= (mask); \
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else \
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RCC->APB1SMENR2 &= ~(mask); \
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(void)RCC->APB1SMENR2; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
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*
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* @param[in] mask APB1 R2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB1R2(mask) { \
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RCC->APB1ENR2 &= ~(mask); \
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RCC->APB1SMENR2 &= ~(mask); \
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(void)RCC->APB1SMENR2; \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus (R2).
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*
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* @param[in] mask APB1 R2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB1R2(mask) { \
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RCC->APB1RSTR2 |= (mask); \
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RCC->APB1RSTR2 &= ~(mask); \
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(void)RCC->APB1RSTR2; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB2(mask, lp) { \
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RCC->APB2ENR |= (mask); \
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if (lp) \
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RCC->APB2SMENR |= (mask); \
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else \
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RCC->APB2SMENR &= ~(mask); \
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(void)RCC->APB2SMENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB2(mask) { \
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RCC->APB2ENR &= ~(mask); \
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RCC->APB2SMENR &= ~(mask); \
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(void)RCC->APB2SMENR; \
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}
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/**
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* @brief Resets one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB2(mask) { \
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RCC->APB2RSTR |= (mask); \
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RCC->APB2RSTR &= ~(mask); \
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(void)RCC->APB2RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB3 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB3(mask, lp) { \
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RCC->APB3ENR |= (mask); \
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if (lp) \
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RCC->APB3SMENR |= (mask); \
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else \
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RCC->APB3SMENR &= ~(mask); \
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(void)RCC->APB3SMENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB3 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB3(mask) { \
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RCC->APB3ENR &= ~(mask); \
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RCC->APB3SMENR &= ~(mask); \
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(void)RCC->APB3SMENR; \
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}
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/**
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* @brief Resets one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB3 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB3(mask) { \
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RCC->APB3RSTR |= (mask); \
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RCC->APB3RSTR &= ~(mask); \
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(void)RCC->APB3RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB1(mask, lp) { \
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RCC->AHB1ENR |= (mask); \
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if (lp) \
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RCC->AHB1SMENR |= (mask); \
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else \
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RCC->AHB1SMENR &= ~(mask); \
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(void)RCC->AHB1SMENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB1(mask) { \
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RCC->AHB1ENR &= ~(mask); \
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RCC->AHB1SMENR &= ~(mask); \
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(void)RCC->AHB1SMENR; \
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}
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/**
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* @brief Resets one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB1(mask) { \
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RCC->AHB1RSTR |= (mask); \
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RCC->AHB1RSTR &= ~(mask); \
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(void)RCC->AHB1RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB2(mask, lp) { \
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RCC->AHB2ENR |= (mask); \
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if (lp) \
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RCC->AHB2SMENR |= (mask); \
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else \
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RCC->AHB2SMENR &= ~(mask); \
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(void)RCC->AHB2SMENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB2(mask) { \
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RCC->AHB2ENR &= ~(mask); \
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RCC->AHB2SMENR &= ~(mask); \
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(void)RCC->AHB2SMENR; \
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}
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/**
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* @brief Resets one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB2(mask) { \
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RCC->AHB2RSTR |= (mask); \
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RCC->AHB2RSTR &= ~(mask); \
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(void)RCC->AHB2RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
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*
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* @param[in] mask AHB3 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB3(mask, lp) { \
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RCC->AHB3ENR |= (mask); \
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if (lp) \
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RCC->AHB3SMENR |= (mask); \
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else \
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RCC->AHB3SMENR &= ~(mask); \
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(void)RCC->AHB3SMENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
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*
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* @param[in] mask AHB3 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB3(mask) { \
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RCC->AHB3ENR &= ~(mask); \
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RCC->AHB3SMENR &= ~(mask); \
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(void)RCC->AHB3SMENR; \
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}
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/**
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* @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
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*
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* @param[in] mask AHB3 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB3(mask) { \
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RCC->AHB3RSTR |= (mask); \
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RCC->AHB3RSTR &= ~(mask); \
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(void)RCC->AHB3RSTR; \
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}
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/** @} */
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/**
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* @name ADC peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the ADC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC1(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
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/**
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* @brief Disables the ADC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC1() rccDisableAHB2(RCC_APB2RSTR_ADCRST)
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/**
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* @brief Resets the ADC1 peripheral.
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*
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* @api
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*/
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#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADCRST)
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/** @} */
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/**
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* @name DAC peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DAC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
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/**
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* @brief Disables the DAC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
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/**
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* @brief Resets the DAC1 peripheral.
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*
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* @api
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*/
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#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
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/** @} */
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/**
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* @name DMA peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
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/**
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* @brief Disables the DMA1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
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/**
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* @brief Resets the DMA1 peripheral.
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*
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* @api
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*/
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#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
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/**
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* @brief Enables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
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/**
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* @brief Disables the DMA2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
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/**
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* @brief Resets the DMA2 peripheral.
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*
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* @api
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*/
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#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
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/** @} */
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/**
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* @name I2C peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the I2C1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
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/**
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* @brief Disables the I2C1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
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/**
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* @brief Resets the I2C1 peripheral.
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*
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* @api
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*/
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#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
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/**
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* @brief Enables the I2C2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
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/**
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* @brief Disables the I2C2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
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/**
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* @brief Resets the I2C2 peripheral.
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*
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* @api
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*/
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#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
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/**
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* @brief Enables the I2C3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
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/**
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* @brief Disables the I2C3 peripheral clock.
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*
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* @api
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*/
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#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
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/**
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* @brief Resets the I2C3 peripheral.
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*
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* @api
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*/
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#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
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/** @} */
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/**
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* @name RNG peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the RNG peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableRNG(lp) rccEnableAHB3(RCC_AHB3ENR_RNGEN, lp)
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/**
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* @brief Disables the RNG peripheral clock.
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*
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* @api
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*/
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#define rccDisableRNG() rccDisableAHB3(RCC_AHB3ENR_RNGEN)
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/**
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* @brief Resets the RNG peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetRNG() rccResetAHB3(RCC_AHB3RSTR_RNGRST)
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/** @} */
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|
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|
/**
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|
* @name SPI peripherals specific RCC operations
|
|
* @{
|
|
*/
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|
/**
|
|
* @brief Enables the SPI1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
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|
|
|
/**
|
|
* @brief Disables the SPI1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
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|
|
|
/**
|
|
* @brief Resets the SPI1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
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|
|
|
/**
|
|
* @brief Enables the SPI2 peripheral clock.
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|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
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|
|
|
/**
|
|
* @brief Resets the SPI2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
|
|
|
|
/**
|
|
* @brief Enables the SPIR peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPIR(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPIR() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
|
|
|
|
/**
|
|
* @brief Resets the SPI2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPIR() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name TIM peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the TIM1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM16 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM16 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM16 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM17 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM17 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM17 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name USART/UART peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USART1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
|
|
|
|
/**
|
|
* @brief Resets the USART1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
|
|
|
|
/**
|
|
* @brief Enables the USART2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
|
|
|
|
/**
|
|
* @brief Resets the USART2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
|
|
|
|
/**
|
|
* @brief Enables the LPUART1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the LPUART1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
|
|
|
|
/**
|
|
* @brief Resets the USART1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name CRC peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the CRC peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the CRC peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
|
|
|
|
/**
|
|
* @brief Resets the CRC peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32_RCC_H */
|
|
|
|
/** @} */
|