260 lines
8.3 KiB
C
260 lines
8.3 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32G4xx/hal_lld.c
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* @brief STM32G4xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief CMSIS system core clock variable.
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* @note It is declared in system_stm32l4xx.h.
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*/
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uint32_t SystemCoreClock = STM32_HCLK;
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing RTC clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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}
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#if STM32_LSE_ENABLED
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/* LSE activation.*/
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Wait until LSE is stable. */
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#endif
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#if HAL_USE_RTC
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#endif /* HAL_USE_RTC */
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/* Low speed output mode.*/
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RCC->BDCR |= STM32_LSCOSEL;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.
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Note, GPIOs are not reset because initialized before this point in
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board files.*/
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rccResetAHB1(~0);
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rccResetAHB2(~STM32_GPIO_EN_MASK);
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rccResetAHB3(~0);
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rccResetAPB1R1(~RCC_APB1RSTR1_PWRRST);
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rccResetAPB1R2(~0);
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rccResetAPB2(~0);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(true);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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/* DMA subsystems initialization.*/
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* IRQ subsystem initialization.*/
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irqInit();
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/* Programmable voltage detector settings.*/
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PWR->CR2 = STM32_PWR_CR2;
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}
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/**
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* @brief STM32L4xx clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
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RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
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#else
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RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
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#endif
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/* Core voltage setup.*/
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PWR->CR1 = STM32_VOS;
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while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
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; /* stable. */
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#if STM32_HSI16_ENABLED
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/* HSI activation.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Wait until HSI16 is stable. */
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#endif
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#if STM32_HSI48_ENABLED
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/* HSI activation.*/
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
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; /* Wait until HSI48 is stable. */
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#endif
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#if STM32_HSE_ENABLED
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#endif
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/* HSE activation.*/
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0)
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; /* Wait until HSE is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Wait until LSI is stable. */
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#endif
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/* Backup domain access enabled and left open.*/
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PWR->CR1 |= PWR_CR1_DBP;
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#if STM32_LSE_ENABLED
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/* LSE activation.*/
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Wait until LSE is stable. */
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLLM and PLLSRC are common to all PLLs.*/
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RCC->PLLCFGR = STM32_PLLPDIV |
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STM32_PLLR | STM32_PLLREN |
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STM32_PLLQ | STM32_PLLQEN |
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STM32_PLLP | STM32_PLLPEN |
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STM32_PLLN | STM32_PLLM |
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STM32_PLLSRC;
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CR |= RCC_CR_PLLON;
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/* Waiting for PLL lock.*/
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while ((RCC->CR & RCC_CR_PLLRDY) == 0)
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;
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#endif
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 |
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STM32_HPRE;
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/* CCIPR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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RCC->CCIPR = STM32_ADC345SEL | STM32_ADC12SEL | STM32_CLK48SEL |
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STM32_FDCANSEL | STM32_I2S23SEL | STM32_SAI1SEL |
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STM32_LPTIM1SEL | STM32_I2C3SEL | STM32_I2C2SEL |
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STM32_I2C1SEL | STM32_LPUART1SEL | STM32_UART5SEL |
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STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
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STM32_USART1SEL;
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/* Set flash WS's for SYSCLK source */
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FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_PRFTEN | STM32_FLASHBITS;
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
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(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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}
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/* Switching to the configured SYSCLK source if it is different from HSI16.*/
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#if STM32_SW != STM32_SW_HSI16
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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/* Wait until SYSCLK is stable.*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
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#endif /* STM32_NO_INIT */
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
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}
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/** @} */
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