158 lines
6.4 KiB
C
158 lines
6.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ports/ARMCM3-STM32F103/stm32_serial.h
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* @brief STM32F103 Serial driver macros and structures.
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* @addtogroup STM32F103_SERIAL
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* @{
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*/
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#ifndef _STM32_SERIAL_H_
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#define _STM32_SERIAL_H_
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/**
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* @brief Serial buffers size.
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* @details Configuration parameter, you can change the depth of the queue
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* buffers depending on the requirements of your application.
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* @note The default is 128 bytes for both the transmission and receive buffers.
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*/
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#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
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#define SERIAL_BUFFERS_SIZE 128
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#endif
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/**
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* @brief Default bit rate.
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* @details Configuration parameter, at startup the USARTs are configured at
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* this speed.
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* @note It is possible to use @p SetUSART() in order to change the working
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* parameters at runtime.
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*/
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#if !defined(DEFAULT_USART_BITRATE) || defined(__DOXYGEN__)
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#define DEFAULT_USART_BITRATE 38400
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#endif
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/**
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* @brief USART1 driver enable switch.
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* @details If set to @p TRUE the support for USART1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(USE_STM32_USART1) || defined(__DOXYGEN__)
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#define USE_STM32_USART1 FALSE
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#endif
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/**
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* @brief USART2 driver enable switch.
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* @details If set to @p TRUE the support for USART2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(USE_STM32_USART2) || defined(__DOXYGEN__)
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#define USE_STM32_USART2 TRUE
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#endif
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/**
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* @brief USART3 driver enable switch.
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* @details If set to @p TRUE the support for USART3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(USE_STM32_USART3) || defined(__DOXYGEN__)
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#define USE_STM32_USART3 FALSE
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#endif
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/*
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* USARTs definitions here.
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*/
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#define SR_PE (1 << 0) /**< @brief SR PE bit.*/
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#define SR_FE (1 << 1) /**< @brief SR FE bit.*/
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#define SR_NE (1 << 2) /**< @brief SR NE bit.*/
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#define SR_ORE (1 << 3) /**< @brief SR ORE bit.*/
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#define SR_IDLE (1 << 4) /**< @brief SR IDLE bit.*/
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#define SR_RXNE (1 << 5) /**< @brief SR RXNE bit.*/
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#define SR_TC (1 << 6) /**< @brief SR TC bit.*/
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#define SR_TXE (1 << 7) /**< @brief SR TXE bit.*/
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#define SR_LBD (1 << 8) /**< @brief SR LBD bit.*/
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#define SR_CTS (1 << 9) /**< @brief SR CTS bit.*/
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#define CR1_SBK (1 << 0) /**< @brief CR1 SBK bit.*/
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#define CR1_RWU (1 << 1) /**< @brief CR1 RWU bit.*/
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#define CR1_RE (1 << 2) /**< @brief CR1 RE bit.*/
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#define CR1_TE (1 << 3) /**< @brief CR1 TE bit.*/
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#define CR1_IDLEIE (1 << 4) /**< @brief CR1 IDLEIE bit.*/
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#define CR1_RXNEIE (1 << 5) /**< @brief CR1 RXNEIE bit.*/
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#define CR1_TCIE (1 << 6) /**< @brief CR1 TCTE bit.*/
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#define CR1_TXEIE (1 << 7) /**< @brief CR1 TXEIE bit.*/
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#define CR1_PEIE (1 << 8) /**< @brief CR1 PEIE bit.*/
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#define CR1_PS (1 << 9) /**< @brief CR1 PS bit.*/
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#define CR1_PCE (1 << 10) /**< @brief CR1 PCE bit.*/
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#define CR1_WAKE (1 << 11) /**< @brief CR1 WAKE bit.*/
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#define CR1_M (1 << 12) /**< @brief CR1 M bit.*/
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#define CR1_UE (1 << 13) /**< @brief CR1 UE bit.*/
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#define CR2_ADD_MASK (15 << 0) /**< @brief CR2 ADD field mask.*/
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#define CR2_LBDL (1 << 5) /**< @brief CR2 LBDL bit.*/
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#define CR2_LBDIE (1 << 6) /**< @brief CR2 LBDIE bit.*/
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#define CR2_CBCL (1 << 8) /**< @brief CR2 CBCL bit.*/
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#define CR2_CPHA (1 << 9) /**< @brief CR2 CPHA bit.*/
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#define CR2_CPOL (1 << 10) /**< @brief CR2 CPOL bit.*/
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#define CR2_CLKEN (1 << 11) /**< @brief CR2 CLKEN bit.*/
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#define CR2_STOP_MASK (3 << 12) /**< @brief CR2 STOP field mask.*/
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#define CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
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#define CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
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#define CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
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#define CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
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#define CR2_LINEN (1 << 14) /**< @brief CR2 LINEN bit.*/
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#define CR3_EIE (1 << 0) /**< @brief CR3 EIE bit.*/
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#define CR3_IREN (1 << 1) /**< @brief CR3 IREN bit.*/
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#define CR3_IRLP (1 << 2) /**< @brief CR3 IRLP bit.*/
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#define CR3_HDSEL (1 << 3) /**< @brief CR3 HDSEL bit.*/
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#define CR3_NACK (1 << 4) /**< @brief CR3 NACK bit.*/
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#define CR3_SCEN (1 << 5) /**< @brief CR3 SCEN bit.*/
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#define CR3_DMAR (1 << 6) /**< @brief CR3 DMAR bit.*/
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#define CR3_DMAT (1 << 7) /**< @brief CR3 DMAT bit.*/
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#define CR3_RTSE (1 << 8) /**< @brief CR3 RTSE bit.*/
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#define CR3_CTSE (1 << 9) /**< @brief CR3 CTSE bit.*/
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#define CR3_CTSIE (1 << 10) /**< @brief CR3 CTSIE bit.*/
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/** @cond never*/
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#if USE_STM32_USART1
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extern FullDuplexDriver COM1;
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#endif
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#if USE_STM32_USART2
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extern FullDuplexDriver COM2;
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#endif
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#if USE_STM32_USART3
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extern FullDuplexDriver COM3;
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#endif
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/** @endcond*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void serial_init(uint32_t prio1, uint32_t prio2, uint32_t prio3);
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void usart_setup(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
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uint16_t cr2, uint16_t cr3);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32_SERIAL_H_ */
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/** @} */
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