544 lines
21 KiB
C
544 lines
21 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32G4xx/stm32_registry.h
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* @brief STM32G4xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef STM32_REGISTRY_H
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#define STM32_REGISTRY_H
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32G4xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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/* RNG attributes.*/
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#define STM32_HAS_RNG1 TRUE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_STORAGE_SIZE 128
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#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
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#define STM32_RTC_WKUP_HANDLER Vector4C
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#define STM32_RTC_ALARM_HANDLER VectorE4
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#define STM32_RTC_TAMP_STAMP_NUMBER 2
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#define STM32_RTC_WKUP_NUMBER 3
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#define STM32_RTC_ALARM_NUMBER 41
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#define STM32_RTC_ALARM_EXTI 18
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#define STM32_RTC_TAMP_STAMP_EXTI 19
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#define STM32_RTC_WKUP_EXTI 20
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#define STM32_RTC_IRQ_ENABLE() do { \
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nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
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nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
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nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
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} while (false)
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0007
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#define STM32_TAMP_CR2_MASK 0x07070007
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#define STM32_TAMP_FLTCR_MASK 0x000000FF
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#define STM32_TAMP_IER_MASK 0x003C0007
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#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
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defined(__DOXYGEN__)
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#define STM32_HAS_HASH1 TRUE
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#define STM32_HAS_CRYP1 TRUE
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#else
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#define STM32_HAS_HASH1 FALSE
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#define STM32_HAS_CRYP1 FALSE
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#endif
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/* RCC attributes.*/
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#define STM32_HAS_HSI16 TRUE
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#define STM32_HAS_HSI48 TRUE
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#define STM32_HAS_MSI FALSE
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#define STM32_HAS_LSI TRUE
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#define STM32_HAS_LSE TRUE
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#define STM32_HAS_HSE TRUE
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#define STM32_HAS_PLL TRUE
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#define STM32_PLL_HAS_P TRUE
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#define STM32_PLL_HAS_Q TRUE
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#define STM32_PLL_HAS_R TRUE
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#define STM32_HAS_PLLSAI1 FALSE
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#define STM32_HAS_PLLSAI2 FALSE
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/* SPI attributes. */
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#define STM32_HAS_SPIR FALSE
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/*===========================================================================*/
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/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */
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/*===========================================================================*/
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#if defined(STM32G473xx) || defined(STM32G483xx) || \
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defined(STM32G474xx) || defined(STM32G484xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_ADC4 TRUE
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#define STM32_HAS_ADC5 TRUE
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 TRUE
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#define STM32_HAS_FDCAN3 TRUE
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#define STM32_FDCAN_FLS_NBR 28U
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#define STM32_FDCAN_FLE_NBR 8U
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#define STM32_FDCAN_RF0_NBR 3U
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#define STM32_FDCAN_RF1_NBR 3U
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#define STM32_FDCAN_RB_NBR 0U
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#define STM32_FDCAN_TEF_NBR 3U
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#define STM32_FDCAN_TB_NBR 3U
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#define STM32_FDCAN_TM_NBR 0U
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 TRUE
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#define STM32_HAS_DAC2_CH2 FALSE
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#define STM32_HAS_DAC3_CH1 TRUE
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#define STM32_HAS_DAC3_CH2 TRUE
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#define STM32_HAS_DAC4_CH1 TRUE
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#define STM32_HAS_DAC4_CH2 TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 8
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#define STM32_DMA2_NUM_CHANNELS 8
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_HAS_CR FALSE
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#define STM32_EXTI_SEPARATE_RF FALSE
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#define STM32_EXTI_NUM_LINES 44
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#define STM32_EXTI_IMR1_MASK 0x1F840000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 2
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN | \
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RCC_AHB2ENR_GPIODEN | \
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RCC_AHB2ENR_GPIOEEN | \
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RCC_AHB2ENR_GPIOFEN | \
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RCC_AHB2ENR_GPIOGEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_HAS_I2C4 TRUE
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/* OCTOSPI attributes.*/
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#define STM32_HAS_OCTOSPI1 FALSE
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#define STM32_HAS_OCTOSPI2 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 FALSE
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#define STM32_HAS_SDMMC2 FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM20 TRUE
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#define STM32_TIM20_IS_32BITS FALSE
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#define STM32_TIM20_CHANNELS 6
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* OTG/USB attributes.*/
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
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#define STM32_USB_PMA_SIZE 1024
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#define STM32_USB_HAS_BCDR TRUE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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/* DCMI attributes.*/
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#define STM32_HAS_DCMI FALSE
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#endif /* defined(STM32G474xx) || defined(STM32G484xx) */
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/*===========================================================================*/
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/* STM32G431xx, STM32G441xx, STM32G471xx. */
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/*===========================================================================*/
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#if defined(STM32G431xx) || defined(STM32G441xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_ADC5 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 FALSE
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#define STM32_HAS_FDCAN3 FALSE
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#define STM32_FDCAN_FLS_NBR 28U
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#define STM32_FDCAN_FLE_NBR 8U
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#define STM32_FDCAN_RF0_NBR 3U
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#define STM32_FDCAN_RF1_NBR 3U
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#define STM32_FDCAN_RB_NBR 0U
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#define STM32_FDCAN_TEF_NBR 3U
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#define STM32_FDCAN_TB_NBR 3U
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#define STM32_FDCAN_TM_NBR 0U
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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#define STM32_HAS_DAC3_CH1 TRUE
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#define STM32_HAS_DAC3_CH2 TRUE
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#define STM32_HAS_DAC4_CH1 FALSE
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#define STM32_HAS_DAC4_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 6
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#define STM32_DMA2_NUM_CHANNELS 6
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_HAS_CR FALSE
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#define STM32_EXTI_SEPARATE_RF FALSE
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#define STM32_EXTI_NUM_LINES 44
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#define STM32_EXTI_IMR1_MASK 0x1F840000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 2
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN | \
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RCC_AHB2ENR_GPIODEN | \
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RCC_AHB2ENR_GPIOEEN | \
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RCC_AHB2ENR_GPIOFEN | \
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RCC_AHB2ENR_GPIOGEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_HAS_I2C4 FALSE
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/* OCTOSPI attributes.*/
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#define STM32_HAS_OCTOSPI1 FALSE
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#define STM32_HAS_OCTOSPI2 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 FALSE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 FALSE
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#define STM32_HAS_SDMMC2 FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* OTG/USB attributes.*/
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
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#define STM32_USB_PMA_SIZE 1024
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#define STM32_USB_HAS_BCDR TRUE
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/* IWDG attributes.*/
|
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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|
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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|
|
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/* DMA2D attributes.*/
|
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#define STM32_HAS_DMA2D FALSE
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|
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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|
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/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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|
|
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/* DCMI attributes.*/
|
|
#define STM32_HAS_DCMI FALSE
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|
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#endif /* defined(STM32G431xx) || defined(STM32G441xx) */
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|
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/** @} */
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|
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#endif /* STM32_REGISTRY_H */
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|
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/** @} */
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