125 lines
5.3 KiB
C
125 lines
5.3 KiB
C
/*
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file SPC563Mxx/hal_lld.c
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* @brief SPC563Mxx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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extern void _vectors(void);
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uint32_t n;
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/* FLASH wait states and prefetching setup.*/
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CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
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CFLASH0.BIUCR2.R = 0;
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CFLASH0.PFCR3.R = 0;
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/* Optimal crossbar settings. The DMA priority is placed above the CPU
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priority in order to not starve I/O activities while the CPU is
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executing tight loops (FLASH and SRAM slave ports only).
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The SRAM is parked on the load/store port, for some unknown reason it
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is defaulted on the instructions port and this kills performance.*/
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XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
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XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
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eDMA (1): 0 (highest)
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Core Instructions (0): 1
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Undocumented (2): 2
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Core Data (4): 3 */
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XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
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eDMA (1): 0 (highest)
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Core Instructions (0): 1
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Undocumented (2): 2
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Core Data (4): 3 */
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/* Downcounter timer initialized for system tick use, TB enabled for debug
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and measurements.*/
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n = SPC5_SYSCLK / CH_FREQUENCY;
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asm volatile ("li %%r3, 0 \t\n"
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"mtspr 284, %%r3 \t\n" /* Clear TBL register. */
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"mtspr 285, %%r3 \t\n" /* Clear TBU register. */
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"mtspr 22, %[n] \t\n" /* Init. DEC register. */
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"mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
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"li %%r3, 0x4000 \t\n" /* TBEN bit. */
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"mtspr 1008, %%r3 \t\n" /* HID0 register. */
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"lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
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"mtspr 340, %%r3" /* TCR register. */
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: : [n] "r" (n) : "r3");
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/* INTC initialization, software vector mode, 4 bytes vectors, starting
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at priority 0.*/
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INTC.MCR.R = 0;
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INTC.CPR.R = 0;
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INTC.IACKR.R = (uint32_t)_vectors;
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}
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/**
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* @brief SPC563 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h and
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* @p hal_lld.h
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* @note This function must be invoked only after the system reset.
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*
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* @special
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*/
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void spc_clock_init(void) {
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#if !SPC5_NO_INIT
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/* PLL activation.*/
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FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
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FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
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#if !SPC5_CLK_BYPASS
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FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
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FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
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FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
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FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
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while (!FMPLL.SYNSR.B.LOCK)
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;
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FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
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#endif /* !SPC5_CLK_BYPASS */
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#endif /* !SPC5_NO_INIT */
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}
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/** @} */
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