115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/hal_lld.h
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* @brief STM32 HAL subsystem low level driver header.
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* @addtogroup STM32_HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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/*
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* Tricks required to make the TRUE/FALSE declaration inside the library
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* compatible.
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*/
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#undef FALSE
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#undef TRUE
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#include "stm32f10x.h"
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#define FALSE 0
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#define TRUE (!FALSE)
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#include "nvic.h"
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#include "stm32_dma.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief System clock setting.
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* @note Only 48MHz and 72MHz are currently supported.
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*/
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#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__)
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#define STM32_SYSCLK 72
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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*/
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#define PLLPRE 1
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#if STM32_SYSCLK == 48
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#define PLLMUL 6
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#elif STM32_SYSCLK == 72
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#define PLLMUL 9
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#else
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#error "unsupported STM32_SYSCLK setting"
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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#define TIMCLK2 (APB2CLK * 2)
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#define TIMCLK1 (APB1CLK * 2)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#if STM32_SYSCLK == 48
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#define USBPREBITS RCC_CFGR_USBPRE
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#define FLASHBITS 0x00000011
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#elif STM32_SYSCLK == 72
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#define USBPREBITS 0
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#define FLASHBITS 0x00000012
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void stm32_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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