178 lines
6.0 KiB
C
178 lines
6.0 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC563/hal_lld.h
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* @brief SPC563 HAL subsystem low level driver header.
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*
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* @addtogroup SPC563_HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "mpc563m.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "SPC563M64"
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#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */
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#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */
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#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */
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#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Clock bypass.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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#if !defined(SPC563_CLK_BYPASS) || defined(__DOXYGEN__)
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#define SPC563_CLK_BYPASS FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC563_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC563_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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* @brief External clock pre-divider.
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* @note Must be in range 0...14.
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* @note The effective divider factor is this value plus one.
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*/
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#if !defined(SPC563_CLK_PREDIV) || defined(__DOXYGEN__)
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#define SPC563_CLK_PREDIV 0
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#endif
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/**
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* @brief Multiplication factor divider.
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* @note Must be in range 32...96.
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*/
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#if !defined(SPC563_CLK_MFD) || defined(__DOXYGEN__)
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#define SPC563_CLK_MFD 40
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#endif
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/**
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* @brief Reduced frequency divider.
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*/
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#if !defined(SPC563_CLK_RFD) || defined(__DOXYGEN__)
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#define SPC563_CLK_RFD RFD_DIV4
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#endif
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/**
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* @brief Flash buffer and prefetching settings.
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* @note Please refer to the SPC563M64 reference manual about the meaning
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* of the following bits, if in doubt DO NOT MODIFY IT.
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* @note Do not specify the APC, WWSC, RWSC bits in this value because
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* those are calculated from the system clock and ORed with this
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* value.
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*/
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#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__)
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#define SPC563_FLASH_BIUCR (0x01110053 & 0xFFFF00FF)
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (SPC563_CLK_PREDIV < 0) || (SPC563_CLK_PREDIV > 14)
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#error "invalid SPC563_CLK_PREDIV value specified"
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#endif
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#if (SPC563_CLK_MFD < 32) || (SPC563_CLK_MFD > 96)
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#error "invalid SPC563_CLK_MFD value specified"
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#endif
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#if (SPC563_CLK_RFD != RFD_DIV2) && (SPC563_CLK_RFD != RFD_DIV4) && \
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(SPC563_CLK_RFD != RFD_DIV8) && (SPC563_CLK_RFD != RFD_DIV16)
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#error "invalid SPC563_CLK_RFD value specified"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#define SPC563_PLLCLK ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD)
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#if (SPC563_PLLCLK < 256000000) || (SPC563_PLLCLK > 512000000)
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#error "VCO frequency out of the acceptable range (256...512)"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#if !SPC563_CLK_BYPASS || defined(__DOXYGEN__)
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#define SPC563_SYSCLK (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1)))
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#else
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#define SPC563_SYSCLK EXTCLK
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#endif
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#if (SPC563_SYSCLK > 80000000) && !SPC563_ALLOW_OVERCLOCK
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#error "System clock above maximum rated frequency (80MHz)"
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#endif
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/**
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* @brief Flash wait states are a function of the system clock.
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*/
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#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__)
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#define SPC563_FLASH_WS 0x00000800 /* APC=0, RWSC=0, WWSC=1. */
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#elif SPC563_SYSCLK <= 60000000
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#define SPC563_FLASH_WS 0x00002900 /* APC=1, RWSC=1, WWSC=1. */
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#else
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#define SPC563_FLASH_WS 0x00004A00 /* APC=2, RWSC=2, WWSC=1. */
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void spc563_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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