115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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#define STM32_I2SCFGR_CHLEN_16BIT (0U << SPI_I2SCFGR_CHLEN_Pos)
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#define STM32_I2SCFGR_CHLEN_32BIT (1U << SPI_I2SCFGR_CHLEN_Pos)
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#define STM32_I2SCFGR_DATLEN_16BIT (0U << SPI_I2SCFGR_DATLEN_Pos)
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#define STM32_I2SCFGR_DATLEN_24BIT (1U << SPI_I2SCFGR_DATLEN_Pos)
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#define STM32_I2SCFGR_DATLEN_32BIT (2U << SPI_I2SCFGR_DATLEN_Pos)
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#define STM32_I2SCFGR_CKPOL_LOW (0U << SPI_I2SCFGR_CKPOL_Pos)
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#define STM32_I2SCFGR_CKPOL_HIGH (1U << SPI_I2SCFGR_CKPOL_Pos)
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#define STM32_I2SCFGR_I2SSTD_I2S (0U << SPI_I2SCFGR_I2SSTD_Pos)
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#define STM32_I2SCFGR_I2SSTD_MSB (1U << SPI_I2SCFGR_I2SSTD_Pos)
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#define STM32_I2SCFGR_I2SSTD_LSB (2U << SPI_I2SCFGR_I2SSTD_Pos)
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#define STM32_I2SCFGR_I2SSTD_PCM (3U << SPI_I2SCFGR_I2SSTD_Pos)
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#define STM32_I2SCFGR_I2SCFG_SLAVE_TX (0U << SPI_I2SCFGR_I2SCFG_Pos)
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#define STM32_I2SCFGR_I2SCFG_SLAVE_RX (1U << SPI_I2SCFGR_I2SCFG_Pos)
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#define STM32_I2SCFGR_I2SCFG_MASTER_TX (2U << SPI_I2SCFGR_I2SCFG_Pos)
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#define STM32_I2SCFGR_I2SCFG_MASTER_RX (3U << SPI_I2SCFGR_I2SCFG_Pos)
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#define STM32_I2SCFGR_I2SMOD_SPI (0U << SPI_I2SCFGR_I2SMOD_Pos)
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#define STM32_I2SCFGR_I2SMOD_I2S (1U << SPI_I2SCFGR_I2SMOD_Pos)
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#define STM32_I2SSPR_ODD_0 (0U << SPI_I2SPR_ODD_Pos)
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#define STM32_I2SSPR_ODD_1 (1U << SPI_I2SPR_ODD_Pos)
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#define I2S_BUF_SIZE 256
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static uint16_t i2s_rx_buf[I2S_BUF_SIZE];
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static void i2scallback(I2SDriver *i2sp);
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static const I2SConfig i2scfg = {
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.tx_buffer = NULL,
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.rx_buffer = i2s_rx_buf,
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.size = I2S_BUF_SIZE,
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.end_cb = i2scallback,
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.i2scfgr = STM32_I2SCFGR_I2SSTD_MSB |
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STM32_I2SCFGR_I2SCFG_MASTER_RX |
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STM32_I2SCFGR_I2SMOD_I2S,
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.i2spr = 0x117 // 1024KHz clock
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};
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static void i2scallback(I2SDriver *i2sp) {
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if (i2sIsBufferComplete(i2sp)) {
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/* 2nd buffer half processing.*/
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}
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else {
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/* 1st buffer half processing.*/
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}
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}
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/*
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* Application entry point.
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*/
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int main(void) {
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/*
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* System initializations.
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* - HAL initialization, this also initializes the configured device drivers
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* and performs the board-specific initializations.
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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*/
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halInit();
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chSysInit();
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/*
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* Starting and configuring the I2S driver.
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*/
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i2sStart(&I2SD2, &i2scfg);
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/* Configure PB13 as I2S_CK.*/
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palSetLineMode(LINE_ARD_A5, PAL_MODE_ALTERNATE(5));
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/* Configure PA10 as I2S_SD.*/
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palSetLineMode(LINE_ARD_A2, PAL_MODE_ALTERNATE(5));
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/*
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* Starting continuous I2S transfer.
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*/
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i2sStartExchange(&I2SD2);
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/*
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* Normal main() thread activity, if the button 1 is pressed then the I2S
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* transfer is stopped.
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*/
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while (true) {
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if (palReadLine(LINE_BUTTON_1) == PAL_LOW) {
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i2sStopExchange(&I2SD2);
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palClearLine(LINE_LED_RED);
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}
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chThdSleepMilliseconds(500);
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}
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return 0;
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}
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