283 lines
11 KiB
C
283 lines
11 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM8L/hal_lld.h
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* @brief STM8L HAL subsystem low level driver source.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - HSECLK (@p 0 if disabled or frequency in Hertz).
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* - HSEBYPASS (@p TRUE if external oscillator rather than a crystal).
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* - LSECLK (@p 0 if disabled or frequency in Hertz).
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* - LSEBYPASS (@p TRUE if external oscillator rather than a crystal).
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* .
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* One of the following macros must also be defined:
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* - STM8L15X_MD for Medium Density devices.
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* - STM8L15X_MDP for Medium Density Plus devices.
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* - STM8L15X_HD for High Density devices.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#undef FALSE
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#undef TRUE
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#include "stm8l15x.h"
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#define FALSE 0
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#define TRUE (!FALSE)
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#if defined (STM8L15X_MD)
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#include "hal_lld_stm8l_md.h"
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#elif defined (STM8L15X_MDP)
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#include "hal_lld_stm8l_mdp.h"
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#elif defined (STM8L15X_HD)
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#include "hal_lld_stm8l_hd.h"
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#else
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#error "unspecified, unsupported or invalid STM8L platform"
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#endif
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "STM8L"
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#define LSICLK 38000 /**< Low speed internal clock. */
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#define HSICLK 16000000 /**< High speed internal clock. */
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#define CLK_SYSSEL_HSI 1 /**< HSI system clock selector. */
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#define CLK_SYSSEL_LSI 2 /**< LSI system clock selector. */
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#define CLK_SYSSEL_HSE 4 /**< HSE system clock selector. */
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#define CLK_SYSSEL_LSE 8 /**< LSE system clock selector. */
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#define CLK_SYSCLK_DIV1 0 /**< Source clock divided by 1. */
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#define CLK_SYSCLK_DIV2 1 /**< Source clock divided by 2. */
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#define CLK_SYSCLK_DIV4 2 /**< Source clock divided by 4. */
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#define CLK_SYSCLK_DIV8 3 /**< Source clock divided by 8. */
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#define CLK_SYSCLK_DIV16 4 /**< Source clock divided by 16. */
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#define CLK_SYSCLK_DIV32 5 /**< Source clock divided by 32. */
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#define CLK_SYSCLK_DIV64 6 /**< Source clock divided by 64. */
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#define CLK_SYSCLK_DIV128 7 /**< Source clock divided by 128. */
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#define CLK_RTCSEL_HSI 1 /**< HSI RTC clock selector. */
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#define CLK_RTCSEL_LSI 2 /**< LSI RTC clock selector. */
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#define CLK_RTCSEL_HSE 4 /**< HSE RTC clock selector. */
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#define CLK_RTCSEL_LSE 8 /**< LSE RTC clock selector. */
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#define CLK_RTCCLK_DIV1 0 /**< Source clock divided by 1. */
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#define CLK_RTCCLK_DIV2 1 /**< Source clock divided by 2. */
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#define CLK_RTCCLK_DIV4 2 /**< Source clock divided by 4. */
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#define CLK_RTCCLK_DIV8 3 /**< Source clock divided by 8. */
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#define CLK_RTCCLK_DIV16 4 /**< Source clock divided by 16. */
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#define CLK_RTCCLK_DIV32 5 /**< Source clock divided by 32. */
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#define CLK_RTCCLK_DIV64 6 /**< Source clock divided by 64. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Disables the clock initialization in the HAL.
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*/
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#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__)
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#define STM8L_NO_CLOCK_INIT FALSE
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#endif
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/**
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* @brief Enables or disables the HSI clock source.
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*/
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#if !defined(STM8L_HSI_ENABLED) || defined(__DOXYGEN__)
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#define STM8L_HSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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#if !defined(STM8L_LSI_ENABLED) || defined(__DOXYGEN__)
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#define STM8L_LSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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*/
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#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__)
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#define STM8L_HSE_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the LSE clock source.
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*/
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#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__)
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#define STM8L_LSE_ENABLED FALSE
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#endif
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/**
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* @brief System clock source selection.
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*/
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#if !defined(STM8L_SYSCLK_SOURCE) || defined(__DOXYGEN__)
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#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI
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#endif
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/**
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* @brief System clock divider.
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*/
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#if !defined(STM8L_SYSCLK_DIVIDER) || defined(__DOXYGEN__)
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#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1
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#endif
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/**
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* @brief RTC clock source selection.
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*/
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#if !defined(STM8L_RTCCLK_SOURCE) || defined(__DOXYGEN__)
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#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_HSI
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#endif
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/**
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* @brief RTC clock divider.
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*/
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#if !defined(STM8L_RTCCLK_DIVIDER) || defined(__DOXYGEN__)
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#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV1) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV2) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV4) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV8) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV16) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV32) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV64) && \
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(STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV128)
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#error "specified invalid SYSCLK divider"
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#endif
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#if (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV1) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV2) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV4) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV8) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV16) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV32) && \
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(STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV64)
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#error "specified invalid RTCCLK divider"
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#endif
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#if STM8L_HSE_ENABLED && (HSECLK == 0)
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#error "impossible to activate HSE"
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#endif
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#if STM8L_LSE_ENABLED && (LSECLK == 0)
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#error "impossible to activate LSE"
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#endif
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#if !STM8L_HSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI) || \
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(STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI))
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#error "requested HSI clock is not enabled"
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#endif
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#if !STM8L_LSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI) || \
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(STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI))
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#error "requested LSI clock is not enabled"
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#endif
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#if !STM8L_HSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE) || \
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(STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE))
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#error "requested HSE clock is not enabled"
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#endif
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#if !STM8L_LSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE) || \
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(STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE))
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#error "requested LSE clock is not enabled"
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#endif
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/**
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* @brief System clock.
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*/
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#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
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#define SYSCLK (HSICLK / 8)
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#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI
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#define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER))
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#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI
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#define SYSCLK (LSICLK / (1 << STM8L_SYSCLK_DIVIDER))
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#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE
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#define SYSCLK (HSECLK / (1 << STM8L_SYSCLK_DIVIDER))
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#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE
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#define SYSCLK (LSECLK / (1 << STM8L_SYSCLK_DIVIDER))
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#else
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#error "specified invalid SYSCLK source"
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#endif
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/**
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* @brief RTC clock.
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*/
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#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
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#define RTCCLK 0
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#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI
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#define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER))
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#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI
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#define RTCCLK (LSICLK / (1 << STM8L_RTCCLK_DIVIDER))
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#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE
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#define RTCCLK (HSECLK / (1 << STM8L_RTCCLK_DIVIDER))
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#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE
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#define RTCCLK (LSECLK / (1 << STM8L_RTCCLK_DIVIDER))
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#else
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#error "specified invalid RTCCLK source"
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#endif
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/**
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* @brief CPU clock.
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* @details On the STM8L the CPU clock is always equal to the system clock.
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*/
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#define CPUCLK SYSCLK
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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