316 lines
9.4 KiB
C
316 lines
9.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/gpt_lld.h
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* @brief STM32 GPT subsystem low level driver header.
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*
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* @addtogroup GPT
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* @{
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*/
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#ifndef _GPT_LLD_H_
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#define _GPT_LLD_H_
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#if HAL_USE_GPT || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief GPTD1 driver enable switch.
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* @details If set to @p TRUE the support for GPTD1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM1 FALSE
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#endif
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/**
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* @brief GPTD2 driver enable switch.
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* @details If set to @p TRUE the support for GPTD2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM2 FALSE
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#endif
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/**
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* @brief GPTD3 driver enable switch.
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* @details If set to @p TRUE the support for GPTD3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM3 FALSE
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#endif
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/**
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* @brief GPTD4 driver enable switch.
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* @details If set to @p TRUE the support for GPTD4 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM4 FALSE
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#endif
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/**
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* @brief GPTD5 driver enable switch.
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* @details If set to @p TRUE the support for GPTD5 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM5 FALSE
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#endif
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/**
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* @brief GPTD8 driver enable switch.
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* @details If set to @p TRUE the support for GPTD8 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__)
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#define STM32_GPT_USE_TIM8 FALSE
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#endif
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/**
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* @brief GPTD1 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM1_IRQ_PRIORITY 7
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#endif
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/**
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* @brief GPTD2 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM2_IRQ_PRIORITY 7
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#endif
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/**
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* @brief GPTD3 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM3_IRQ_PRIORITY 7
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#endif
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/**
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* @brief GPTD4 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#endif
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/**
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* @brief GPTD5 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM5_IRQ_PRIORITY 7
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#endif
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/**
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* @brief GPTD5 interrupt priority level setting.
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*/
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#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_GPT_TIM8_IRQ_PRIORITY 7
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1
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#error "TIM1 not present in the selected device"
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#endif
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#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2
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#error "TIM2 not present in the selected device"
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#endif
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#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3
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#error "TIM3 not present in the selected device"
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#endif
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#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4
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#error "TIM4 not present in the selected device"
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#endif
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#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5
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#error "TIM5 not present in the selected device"
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#endif
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#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8
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#error "TIM8 not present in the selected device"
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#endif
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#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \
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!STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \
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!STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM8
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#error "GPT driver activated but no TIM peripheral assigned"
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#endif
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#if STM32_GPT_USE_TIM1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM1"
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#endif
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#if STM32_GPT_USE_TIM2 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM2"
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#endif
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#if STM32_GPT_USE_TIM3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM3"
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#endif
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#if STM32_GPT_USE_TIM4 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM4"
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#endif
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#if STM32_GPT_USE_TIM5 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM5"
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#endif
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#if STM32_GPT_USE_TIM8 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM8"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief GPT frequency type.
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*/
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typedef uint32_t gptfreq_t;
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/**
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* @brief GPT counter type.
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*/
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typedef uint16_t gptcnt_t;
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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/**
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* @brief Timer clock in Hz.
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* @note The low level can use assertions in order to catch invalid
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* frequency specifications.
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*/
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gptfreq_t frequency;
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/**
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* @brief Timer callback pointer.
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* @note This callback is invoked on GPT counter events.
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*/
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gptcallback_t callback;
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/* End of the mandatory fields.*/
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} GPTConfig;
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/**
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* @brief Structure representing a GPT driver.
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*/
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struct GPTDriver {
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/**
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* @brief Driver state.
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*/
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gptstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const GPTConfig *config;
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#if defined(GPT_DRIVER_EXT_FIELDS)
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GPT_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Timer base clock.
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*/
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uint32_t clock;
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/**
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* @brief Pointer to the TIMx registers block.
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*/
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stm32_tim_t *tim;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD1;
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#endif
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#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD2;
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#endif
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#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD3;
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#endif
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#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD4;
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#endif
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#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD5;
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#endif
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#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__)
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extern GPTDriver GPTD8;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void gpt_lld_init(void);
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void gpt_lld_start(GPTDriver *gptp);
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void gpt_lld_stop(GPTDriver *gptp);
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void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
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void gpt_lld_stop_timer(GPTDriver *gptp);
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void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_GPT */
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#endif /* _GPT_LLD_H_ */
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/** @} */
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