417 lines
12 KiB
C
417 lines
12 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ports/ARM7-AT91SAM7X/sam7x_emac.c
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* @brief AT91SAM7X EMAC driver code.
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* @addtogroup AT91SAM7X_EMAC
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* @{
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*/
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#include <string.h>
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#include <ch.h>
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#include "board.h"
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#include "sam7x_emac.h"
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#include "mii.h"
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#include "at91lib/aic.h"
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EventSource EMACFrameTransmitted; /* A frame was transmitted. */
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EventSource EMACFrameReceived; /* A frame was received. */
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#ifndef __DOXYGEN__
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//static int received; /* Buffered frames counter. */
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static bool_t link_up; /* Last from EMACGetLinkStatus()*/
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static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10};
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static BufDescriptorEntry rent[EMAC_RECEIVE_BUFFERS] __attribute__((aligned(8)));
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static uint8_t rbuffers[EMAC_RECEIVE_BUFFERS * EMAC_RECEIVE_BUFFERS_SIZE] __attribute__((aligned(8)));
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static BufDescriptorEntry *rxptr;
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static BufDescriptorEntry tent[EMAC_TRANSMIT_BUFFERS] __attribute__((aligned(8)));
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static uint8_t tbuffers[EMAC_TRANSMIT_BUFFERS * EMAC_TRANSMIT_BUFFERS_SIZE] __attribute__((aligned(8)));
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static BufDescriptorEntry *txptr;
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#endif
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#define AT91C_PB15_ERXDV AT91C_PB15_ERXDV_ECRSDV
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#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK | \
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AT91C_PB1_ETXEN | AT91C_PB2_ETX0 | \
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AT91C_PB3_ETX1 | AT91C_PB4_ECRS | \
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AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \
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AT91C_PB7_ERXER | AT91C_PB8_EMDC | \
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AT91C_PB9_EMDIO | AT91C_PB10_ETX2 | \
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AT91C_PB11_ETX3 | AT91C_PB12_ETXER | \
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AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \
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AT91C_PB15_ERXDV | AT91C_PB16_ECOL | \
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AT91C_PB17_ERXCK)
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#define PHY_LATCHED_PINS (AT91C_PB4_ECRS | AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \
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AT91C_PB7_ERXER | AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \
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AT91C_PB15_ERXDV | AT91C_PB16_ECOL | PIOB_PHY_IRQ)
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/*
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* PHY utilities.
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*/
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static uint32_t phy_get(uint8_t regno) {
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AT91C_BASE_EMAC->EMAC_MAN = (1 << 30) | // SOF = 01
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(2 << 28) | // RW = 10
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(PHY_ADDRESS << 23) |
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(regno << 18) |
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(2 << 16); // CODE = 10
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while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
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;
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return AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF;
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}
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/*static void phy_put(uint8_t regno, uint32_t val) {
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AT91C_BASE_EMAC->EMAC_MAN = (1 << 30) | // SOF = 01
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(1 << 28) | // RW = 01
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(PHY_ADDRESS << 23) |
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(regno << 18) |
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(2 << 16) | // CODE = 10
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val;
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while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
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;
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}*/
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#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR)
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#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \
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AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND)
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__attribute__((noinline))
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static void ServeInterrupt(void) {
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uint32_t isr, rsr, tsr;
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/* Fix for the EMAC errata */
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isr = AT91C_BASE_EMAC->EMAC_ISR;
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rsr = AT91C_BASE_EMAC->EMAC_RSR;
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tsr = AT91C_BASE_EMAC->EMAC_TSR;
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if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) {
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if (rsr & AT91C_EMAC_REC) {
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// received++;
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chSysLockFromIsr();
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chEvtBroadcastI(&EMACFrameReceived);
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chSysUnlockFromIsr();
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}
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AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS;
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}
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if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) {
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if (tsr & AT91C_EMAC_COMP) {
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chSysLockFromIsr();
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chEvtBroadcastI(&EMACFrameTransmitted);
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chSysUnlockFromIsr();
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}
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AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS;
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}
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AT91C_BASE_AIC->AIC_EOICR = 0;
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}
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CH_IRQ_HANDLER(EMACIrqHandler) {
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CH_IRQ_PROLOGUE();
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ServeInterrupt();
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CH_IRQ_EPILOGUE();
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}
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/*
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* EMAC subsystem initialization.
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*/
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void emac_init(int prio) {
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int i;
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/*
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* Buffers initialization.
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*/
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// received = 0;
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for (i = 0; i < EMAC_RECEIVE_BUFFERS; i++) {
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rent[i].w1 = (uint32_t)&rbuffers[i * EMAC_RECEIVE_BUFFERS_SIZE];
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rent[i].w2 = 0;
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}
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rent[EMAC_RECEIVE_BUFFERS - 1].w1 |= W1_R_WRAP;
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rxptr = rent;
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for (i = 0; i < EMAC_TRANSMIT_BUFFERS; i++) {
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tent[i].w1 = (uint32_t)&tbuffers[i * EMAC_TRANSMIT_BUFFERS_SIZE];
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tent[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_USED;
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}
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tent[EMAC_TRANSMIT_BUFFERS - 1].w2 |= W2_T_WRAP;
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txptr = tent;
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/*
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* Disables the pullups on all the pins that are latched on reset by the PHY.
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* The status latched into the PHY is:
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* PHYADDR = 00001
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* PCS_LPBK = 0 (disabled)
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* ISOLATE = 0 (disabled)
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* RMIISEL = 0 (MII mode)
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* RMIIBTB = 0 (BTB mode disabled)
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* SPEED = 1 (100mbps)
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* DUPLEX = 1 (full duplex)
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* ANEG_EN = 1 (auto negotiation enabled)
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*/
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AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS;
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/*
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* PHY power control.
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*/
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AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD; // Becomes an output.
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AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD; // Default pullup disabled.
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AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD; // Output to high level.
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/*
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* PHY reset by pulsing the NRST pin.
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*/
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AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100;
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AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
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while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
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;
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/*
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* EMAC pins setup and clock enable. Note, PB18 is not included because it is
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* used as #PD control and not as EF100.
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*/
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
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AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK;
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AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK;
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AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK;
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/*
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* EMAC setup.
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*/
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AT91C_BASE_EMAC->EMAC_NCR = 0; // Initial setting.
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AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10; // MDC-CLK = MCK / 32
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AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN; // Enable EMAC in MII mode
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AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rent; // RX buffers list
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AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)tent; // TX buffers list
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AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR |
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AT91C_EMAC_REC |
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AT91C_EMAC_BNA; // Clears RSR
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AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS; // Initial NCFGR settings
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE |
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AT91C_EMAC_RE |
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AT91C_EMAC_CLRSTAT; // Initial NCR settings
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EMACSetAddress(default_mac);
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/*
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* PHY detection and settings.
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*/
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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if ((phy_get(MII_PHYSID1) != (MII_MICREL_ID >> 16)) ||
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((phy_get(MII_PHYSID2) & 0xFFF0) != (MII_MICREL_ID & 0xFFF0)))
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chSysHalt();
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/*
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* Waits for auto-negotiation to end and then detects the link status.
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*/
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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/*
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* Interrupt setup.
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*/
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AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
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AIC_ConfigureIT(AT91C_ID_EMAC,
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AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | prio,
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EMACIrqHandler);
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AIC_EnableIT(AT91C_ID_EMAC);
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/*
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* Event sources setup.
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*/
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chEvtInit(&EMACFrameTransmitted);
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chEvtInit(&EMACFrameReceived);
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}
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/*
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* Set the MAC address.
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*/
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void EMACSetAddress(const uint8_t *eaddr) {
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AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((eaddr[3] << 24) | (eaddr[2] << 16) |
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(eaddr[1] << 8) | eaddr[0]);
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AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((eaddr[5] << 8) | eaddr[4]);
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}
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/*
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* Returns TRUE if the link is active. To be invoked at regular intervals in
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* order to monitor the link.
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* @note It is not thread-safe.
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*/
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bool_t EMACGetLinkStatus(void) {
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uint32_t ncfgr, bmsr, bmcr, lpa;
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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(void)phy_get(MII_BMSR);
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bmsr = phy_get(MII_BMSR);
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if (!(bmsr & BMSR_LSTATUS)) {
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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return link_up = FALSE;
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}
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ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
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bmcr = phy_get(MII_BMCR);
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if (bmcr & BMCR_ANENABLE) {
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lpa = phy_get(MII_LPA);
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if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
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ncfgr |= AT91C_EMAC_SPD;
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if (lpa & (LPA_10FULL | LPA_100FULL))
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ncfgr |= AT91C_EMAC_FD;
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}
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else {
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if (bmcr & BMCR_SPEED100)
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ncfgr |= AT91C_EMAC_SPD;
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if (bmcr & BMCR_FULLDPLX)
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ncfgr |= AT91C_EMAC_FD;
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}
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AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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return link_up = TRUE;
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}
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/*
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* Allocates and locks a buffer for a transmission operation.
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*/
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BufDescriptorEntry *EMACGetTransmitBuffer(void) {
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BufDescriptorEntry *cptr;
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if (!link_up)
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return NULL;
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chSysLock();
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cptr = txptr;
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if (!(cptr->w2 & W2_T_USED) ||
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(cptr->w2 & W2_T_LOCKED)) {
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chSysUnlock();
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return FALSE;
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}
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cptr->w2 |= W2_T_LOCKED; /* Locks the buffer while copying.*/
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if (++txptr >= &tent[EMAC_TRANSMIT_BUFFERS])
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txptr = tent;
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chSysUnlock();
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return cptr;
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}
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/*
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* Transmits a previously allocated buffer and then releases it.
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*/
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void EMACTransmit(BufDescriptorEntry *cptr, size_t size) {
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chDbgAssert(size <= EMAC_TRANSMIT_BUFFERS_SIZE, "sam7x_emac.c, EMACTransmit");
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chSysLock();
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if (cptr < &tent[EMAC_TRANSMIT_BUFFERS - 1])
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cptr->w2 = size | W2_T_LAST_BUFFER;
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else
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cptr->w2 = size | W2_T_LAST_BUFFER | W2_T_WRAP;
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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chSysUnlock();
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}
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/*
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* Reads a buffered frame.
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* Returns TRUE if a frame was present and read else FALSE.
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* @note It is not thread-safe.
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*/
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bool_t EMACReceive(uint8_t *buf, size_t *sizep) {
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unsigned n;
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size_t size;
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uint8_t *p;
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bool_t overflow, found;
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// chSysLock();
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// if (received <= 0) {
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// chSysUnlock();
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// return FALSE;
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// }
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// received--;
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// chSysUnlock();
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n = EMAC_RECEIVE_BUFFERS;
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/*
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* Skips unused buffers, if any.
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*/
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skip:
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while (n && !(rxptr->w1 & W1_R_OWNERSHIP)) {
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if (++rxptr >= &rent[EMAC_RECEIVE_BUFFERS])
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rxptr = rent;
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n--;
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}
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/*
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* Skips fragments, if any.
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*/
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while (n && (rxptr->w1 & W1_R_OWNERSHIP) && !(rxptr->w2 & W2_R_FRAME_START)) {
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rxptr->w1 &= ~W1_R_OWNERSHIP;
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if (++rxptr >= &rent[EMAC_RECEIVE_BUFFERS])
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rxptr = rent;
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n--;
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}
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restart:
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p = buf;
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size = 0;
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found = overflow = FALSE;
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while (n && !found) {
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size_t segsize;
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if (!(rxptr->w1 & W1_R_OWNERSHIP))
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goto skip; /* Empty buffer for some reason... */
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if (size && (rxptr->w2 & W2_R_FRAME_START))
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goto restart; /* Another start buffer for some reason... */
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if (rxptr->w2 & W2_R_FRAME_END) {
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segsize = (rxptr->w2 & W2_T_LENGTH_MASK) - size;
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if (((rxptr->w2 & W2_T_LENGTH_MASK) > *sizep) ||
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(segsize > EMAC_RECEIVE_BUFFERS_SIZE))
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overflow = TRUE;
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found = TRUE;
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}
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else {
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segsize = EMAC_RECEIVE_BUFFERS_SIZE;
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if (size + segsize > *sizep)
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overflow = TRUE;
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}
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if (!overflow) {
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chDbgAssert(segsize <= 128, "sam7x_emac.c, EMACReceive()")
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memcpy(p, (void *)(rxptr->w1 & W1_R_ADDRESS_MASK), segsize);
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p += segsize;
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size += segsize;
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}
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rxptr->w1 &= ~W1_R_OWNERSHIP;
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if (++rxptr >= &rent[EMAC_RECEIVE_BUFFERS])
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rxptr = rent;
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n--;
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}
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*sizep = size;
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return found && !overflow;
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}
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/** @} */
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