138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include <avr/io.h>
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/*
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* All inputs with pullups.
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*/
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#define VAL_DDRA 0x00
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#define VAL_PORTA 0xFF
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/*
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* All inputs with pullups.
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*/
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#define VAL_DDRB 0x00
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#define VAL_PORTB 0xFF
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/*
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* All inputs with pullups.
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*/
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#define VAL_DDRC 0x00
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#define VAL_PORTC 0xFF
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/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
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* IN IN OUT IN OUT IN IN IN
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* DDRD 0 0 1 0 1 0 0 0
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* PU HiZ VAL PU VAL HiZ HiZ HiZ
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* PORTD 1 0 ?1 1 1 0 0 0
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*/
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#define VAL_DDRD 0x28
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#define VAL_PORTD 0xB8
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/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0
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* IN IN IN OUT IN IN OUT IN
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* DDRE 0 0 0 1 0 0 1 0
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* PU PU HiZ VAL PU PU VAL HiZ
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* PORTE 1 1 0 1 1 1 1 0
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*/
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#define VAL_DDRE 0x12
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#define VAL_PORTE 0xDE
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/* TDI TDO TMS TCK PF3 PF2 PF1 PF0
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* x x x x IN IN IN IN
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* DDRF 0 0 0 0 0 0 0 0
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* x x x x PU PU PU PU
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* PORTF 0 0 0 0 1 1 1 1
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*
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*/
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#define VAL_DDRF 0x00
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#define VAL_PORTF 0x0F
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/* x x x x x PG2 PG1 PG0
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* x x x x x IN IN IN
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* DDRG 0 0 0 0 0 0 0 0
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* x x x x x PU PU PU
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* PORTG 0 0 0 0 0 1 1 1
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*
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*/
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#define VAL_DDRG 0x00
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#define VAL_PORTG 0x07
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void hwinit(void) {
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/*
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* I/O ports setup.
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*/
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DDRA = VAL_DDRA;
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PORTA = VAL_PORTA;
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DDRB = VAL_DDRB;
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PORTB = VAL_PORTB;
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DDRC = VAL_DDRC;
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PORTC = VAL_PORTC;
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DDRD = VAL_DDRD;
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PORTD = VAL_PORTD;
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DDRE = VAL_DDRE;
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PORTE = VAL_PORTE;
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DDRF = VAL_DDRF;
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PORTF = VAL_PORTF;
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DDRG = VAL_DDRG;
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PORTG = VAL_PORTG;
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/*
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* External interrupts setup, all disabled initially.
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*/
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EICRA = 0x00;
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EICRB = 0x00;
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EIMSK = 0x00;
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/*
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* Enables Idle mode for SLEEP instruction.
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*/
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SMCR = 1;
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/*
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* Timer 0 setup.
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*/
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TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode.
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(0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O).
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(0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source.
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OCR0A = F_CPU / 64 / CH_FREQUENCY - 1;
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TCNT0 = 0; // Reset counter.
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TIFR0 = (1 << OCF0A); // Reset pending (if any).
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TIMSK0 = (1 << OCIE0A); // Interrupt on compare.
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}
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void _IdleThread(void *p) {
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while (TRUE) {
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// asm volatile ("sleep");
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}
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}
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void chSysHalt(void) {
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chSysLock();
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while (TRUE)
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;
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}
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