1679 lines
39 KiB
C
1679 lines
39 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F7xx/stm32_rcc.h
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* @brief RCC helper driver header.
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* @note This file requires definitions from the ST header file
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* @p stm32f7xx.h.
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*
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* @addtogroup STM32F7xx_RCC
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* @{
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*/
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#ifndef _STM32_RCC_
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#define _STM32_RCC_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Generic RCC operations
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* @{
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*/
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, low set
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1L(mask, lp) { \
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RCC->APB1LENR |= (mask); \
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if (lp) \
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RCC->APB1LLPENR |= (mask); \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, high set
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1H(mask, lp) { \
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RCC->APB1HENR |= (mask); \
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if (lp) \
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RCC->APB1HLPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, low set
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*
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* @api
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*/
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#define rccDisableAPB1L(mask) { \
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RCC->APB1LENR &= ~(mask); \
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RCC->APB1LLPENR &= ~(mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, high set
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*
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* @api
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*/
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#define rccDisableAPB1H(mask) { \
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RCC->APB1HENR &= ~(mask); \
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RCC->APB1HLPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, low set
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*
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* @api
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*/
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#define rccResetAPB1L(mask) { \
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RCC->APB1LRSTR |= (mask); \
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RCC->APB1LRSTR = 0; \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask, high set
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*
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* @api
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*/
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#define rccResetAPB1H(mask) { \
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RCC->APB1HRSTR |= (mask); \
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RCC->APB1HRSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB2(mask, lp) { \
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RCC->APB2ENR |= (mask); \
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if (lp) \
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RCC->APB2LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB2(mask) { \
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RCC->APB2ENR &= ~(mask); \
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RCC->APB2LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB2(mask) { \
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RCC->APB2RSTR |= (mask); \
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RCC->APB2RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB3 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB3(mask, lp) { \
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RCC->APB3ENR |= (mask); \
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if (lp) \
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RCC->APB3LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB3 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB3(mask) { \
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RCC->APB3ENR &= ~(mask); \
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RCC->APB3LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB3 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB3(mask) { \
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RCC->APB3RSTR |= (mask); \
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RCC->APB3RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB4 bus.
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*
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* @param[in] mask APB4 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB4(mask, lp) { \
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RCC->APB4ENR |= (mask); \
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if (lp) \
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RCC->APB4LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB4 bus.
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*
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* @param[in] mask APB4 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB4(mask) { \
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RCC->APB4ENR &= ~(mask); \
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RCC->APB4LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB4 bus.
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*
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* @param[in] mask APB4 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB4(mask) { \
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RCC->APB4RSTR |= (mask); \
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RCC->APB4RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB1(mask, lp) { \
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RCC->AHB1ENR |= (mask); \
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if (lp) \
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RCC->AHB1LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB1(mask) { \
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RCC->AHB1ENR &= ~(mask); \
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RCC->AHB1LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the AHB1 bus.
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*
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* @param[in] mask AHB1 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB1(mask) { \
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RCC->AHB1RSTR |= (mask); \
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RCC->AHB1RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB2(mask, lp) { \
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RCC->AHB2ENR |= (mask); \
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if (lp) \
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RCC->AHB2LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB2(mask) { \
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RCC->AHB2ENR &= ~(mask); \
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RCC->AHB2LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the AHB2 bus.
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*
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* @param[in] mask AHB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB2(mask) { \
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RCC->AHB2RSTR |= (mask); \
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RCC->AHB2RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB3 bus.
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*
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* @param[in] mask AHB3 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB3(mask, lp) { \
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RCC->AHB3ENR |= (mask); \
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if (lp) \
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RCC->AHB3LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB3 bus.
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*
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* @param[in] mask AHB3 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB3(mask) { \
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RCC->AHB3ENR &= ~(mask); \
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RCC->AHB3LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the AHB3 bus.
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*
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* @param[in] mask AHB3 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB3(mask) { \
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RCC->AHB3RSTR |= (mask); \
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RCC->AHB3RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB4 bus.
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*
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* @param[in] mask AHB4 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB4(mask, lp) { \
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RCC->AHB4ENR |= (mask); \
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if (lp) \
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RCC->AHB4LPENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB4 bus.
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*
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* @param[in] mask AHB4 peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB4(mask) { \
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RCC->AHB4ENR &= ~(mask); \
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RCC->AHB4LPENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the AHB4 bus.
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*
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* @param[in] mask AHB4 peripherals mask
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*
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* @api
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*/
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#define rccResetAHB4(mask) { \
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RCC->AHB4RSTR |= (mask); \
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RCC->AHB4RSTR = 0; \
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}
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/** @} */
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/**
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* @name ADC peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the ADC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
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/**
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* @brief Disables the ADC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
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/**
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* @brief Resets the ADC1 peripheral.
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*
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* @api
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*/
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#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
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/**
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* @brief Enables the ADC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)
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/**
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* @brief Disables the ADC2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
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/**
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* @brief Resets the ADC2 peripheral.
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*
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* @api
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*/
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#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
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/**
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* @brief Enables the ADC3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)
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/**
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* @brief Disables the ADC3 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
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/**
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* @brief Resets the ADC3 peripheral.
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*
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* @api
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*/
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#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
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/** @} */
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/**
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* @name DAC peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DAC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC1(lp) rccEnableAPB1L(RCC_APB1LENR_DACEN, lp)
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/**
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* @brief Disables the DAC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC1() rccDisableAPB1L(RCC_APB1LENR_DACEN)
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/**
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* @brief Resets the DAC1 peripheral.
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*
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* @api
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*/
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#define rccResetDAC1() rccResetAPB1L(RCC_APB1LRSTR_DACRST)
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/** @} */
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/**
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* @name DMA peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the BDMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableBDMA1(lp) rccEnableAHB4(RCC_AHB4ENR_BDMAEN, lp)
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/**
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* @brief Disables the BDMA1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableBDMA1() rccDisableAHB4(RCC_AHB4ENR_BDMAEN)
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/**
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* @brief Resets the BDMA1 peripheral.
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*
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* @api
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*/
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#define rccResetBDMA1() rccEnableAHB4(RCC_AHB4RSTR_BDMARST)
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/**
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* @brief Enables the DMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
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/**
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* @brief Disables the DMA1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
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/**
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* @brief Resets the DMA1 peripheral.
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*
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* @api
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*/
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#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
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/**
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* @brief Enables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
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/**
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* @brief Disables the DMA2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
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/**
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* @brief Resets the DMA2 peripheral.
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*
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* @api
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*/
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#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
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/** @} */
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/**
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* @name RAM specific RCC operations
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* @{
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*/
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|
/**
|
|
* @brief Enables the BKPRAM clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableBKPRAM(lp) rccEnableAHB4(RCC_AHB4ENR_BKPRAMEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the BKPRAM clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableBKPRAM() rccDisableAHB4(RCC_AHB4ENR_BKPRAMEN)
|
|
|
|
/**
|
|
* @brief Enables the SRAM1 clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSRAM1(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SRAM1 clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSRAM1() rccDisableAHB2(RCC_AHB2ENR_D2SRAM1EN)
|
|
|
|
/**
|
|
* @brief Enables the SRAM2 clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSRAM2(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SRAM2 clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSRAM2() rccDisableAHB2(RCC_AHB2ENR_D2SRAM2EN)
|
|
|
|
/**
|
|
* @brief Enables the SRAM3 clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSRAM3(lp) rccEnableAHB2(RCC_AHB2ENR_D2SRAM3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SRAM3 clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSRAM3() rccDisableAHB2(RCC_AHB2ENR_D2SRAM3EN)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name ETH peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the ETH peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
|
|
RCC_AHB1ENR_ETHMACTXEN | \
|
|
RCC_AHB1ENR_ETHMACRXEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the ETH peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableETH(...) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
|
|
RCC_AHB1ENR_ETHMACTXEN | \
|
|
RCC_AHB1ENR_ETHMACRXEN)
|
|
|
|
/**
|
|
* @brief Resets the ETH peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name I2C peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the I2C1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableI2C1(lp) rccEnableAPB1L(RCC_APB1LENR_I2C1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the I2C1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableI2C1() rccDisableAPB1L(RCC_APB1LENR_I2C1EN)
|
|
|
|
/**
|
|
* @brief Resets the I2C1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetI2C1() rccResetAPB1L(RCC_APB1LRSTR_I2C1RST)
|
|
|
|
/**
|
|
* @brief Enables the I2C2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableI2C2(lp) rccEnableAPB1L(RCC_APB1LENR_I2C2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the I2C2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableI2C2() rccDisableAPB1L(RCC_APB1LENR_I2C2EN)
|
|
|
|
/**
|
|
* @brief Resets the I2C2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetI2C2() rccResetAPB1L(RCC_APB1LRSTR_I2C2RST)
|
|
|
|
/**
|
|
* @brief Enables the I2C3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableI2C3(lp) rccEnableAPB1L(RCC_APB1LENR_I2C3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the I2C3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableI2C3() rccDisableAPB1L(RCC_APB1LENR_I2C3EN)
|
|
|
|
/**
|
|
* @brief Resets the I2C3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetI2C3() rccResetAPB1L(RCC_APB1LRSTR_I2C3RST)
|
|
|
|
/**
|
|
* @brief Enables the I2C4 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableI2C4(lp) rccEnableAPB4(RCC_APB4ENR_I2C4EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the I2C4 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableI2C4() rccDisableAPB4(RCC_APB4ENR_I2C4EN)
|
|
|
|
/**
|
|
* @brief Resets the I2C4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetI2C4() rccResetAPB4(RCC_APB4RSTR_I2C4RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name OTG peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USB1_OTG_HS peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB1_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB1_OTG_HS peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB1_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSEN)
|
|
|
|
/**
|
|
* @brief Resets the USB1_OTG_HS peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSB1_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB1OTGHSRST)
|
|
|
|
/**
|
|
* @brief Enables the USB2_OTG_HS peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB2_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB2_OTG_HS peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB2_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSEN)
|
|
|
|
/**
|
|
* @brief Resets the USB2_OTG_HS peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSB2_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGHSRST)
|
|
|
|
/**
|
|
* @brief Enables the USB1_OTG_HS ULPI peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB1_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB1_OTG_HS peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB1_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN)
|
|
|
|
/**
|
|
* @brief Enables the USB2_OTG_HS ULPI peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB2_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB2_OTG_HS peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB2_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name QUADSPI peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the QUADSPI1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the QUADSPI1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
|
|
|
|
/**
|
|
* @brief Resets the QUADSPI1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SDMMC peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the SDMMC1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSDMMC1(lp) rccEnableAHB3(RCC_AHB3ENR_SDMMC1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SDMMC1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSDMMC1() rccDisableAHB3(RCC_AHB3ENR_SDMMC1EN)
|
|
|
|
/**
|
|
* @brief Resets the SDMMC1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSDMMC1() rccResetAHB3(RCC_AHB3RSTR_SDMMC1RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the SPI1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
|
|
|
|
/**
|
|
* @brief Enables the SPI2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI2(lp) rccEnableAPB1L(RCC_APB1LENR_SPI2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI2() rccDisableAPB1L(RCC_APB1LENR_SPI2EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI2() rccResetAPB1L(RCC_APB1LRSTR_SPI2RST)
|
|
|
|
/**
|
|
* @brief Enables the SPI3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI3(lp) rccEnableAPB1L(RCC_APB1LENR_SPI3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI3() rccDisableAPB1L(RCC_APB1LENR_SPI3EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI3() rccResetAPB1L(RCC_APB1LRSTR_SPI3RST)
|
|
|
|
/**
|
|
* @brief Enables the SPI4 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI4 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
|
|
|
|
/**
|
|
* @brief Enables the SPI5 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI5 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI5 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)
|
|
|
|
/**
|
|
* @brief Enables the SPI6 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableSPI6(lp) rccEnableAPB4(RCC_APB4ENR_SPI6EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the SPI6 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableSPI6() rccDisableAPB4(RCC_APB4ENR_SPI6EN)
|
|
|
|
/**
|
|
* @brief Resets the SPI6 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetSPI6() rccResetAPB4(RCC_APB4RSTR_SPI6RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name TIM peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the TIM1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM1(...) rccDisableAPB2(RCC_APB2ENR_TIM1EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM2(lp) rccEnableAPB1L(RCC_APB1LENR_TIM2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM2(...) rccDisableAPB1L(RCC_APB1LENR_TIM2EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM2() rccResetAPB1L(RCC_APB1LRSTR_TIM2RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM3(lp) rccEnableAPB1L(RCC_APB1LENR_TIM3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM3(...) rccDisableAPB1L(RCC_APB1LENR_TIM3EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM3() rccResetAPB1L(RCC_APB1LRSTR_TIM3RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM4 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM4(lp) rccEnableAPB1L(RCC_APB1LENR_TIM4EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM4 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM4(...) rccDisableAPB1L(RCC_APB1LENR_TIM4EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM4() rccResetAPB1L(RCC_APB1LRSTR_TIM4RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM5 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM5(lp) rccEnableAPB1L(RCC_APB1LENR_TIM5EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM5 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM5(lp) rccDisableAPB1L(RCC_APB1LENR_TIM5EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM5 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM5() rccResetAPB1L(RCC_APB1LRSTR_TIM5RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM6 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM6(lp) rccEnableAPB1L(RCC_APB1LENR_TIM6EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM6 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM6(...) rccDisableAPB1L(RCC_APB1LENR_TIM6EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM6 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM6() rccResetAPB1L(RCC_APB1LRSTR_TIM6RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM7 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM7(lp) rccEnableAPB1L(RCC_APB1LENR_TIM7EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM7 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM7(...) rccDisableAPB1L(RCC_APB1LENR_TIM7EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM7 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM7() rccResetAPB1L(RCC_APB1LRSTR_TIM7RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM8 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM8 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM8(...) rccDisableAPB2(RCC_APB2ENR_TIM8EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM8 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM12 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM12(lp) rccEnableAPB1L(RCC_APB1LENR_TIM12EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM12 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM12(...) rccDisableAPB1L(RCC_APB1LENR_TIM12EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM12 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM12() rccResetAPB1L(RCC_APB1LRSTR_TIM12RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM13 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM13(lp) rccEnableAPB1L(RCC_APB1LENR_TIM13EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM13 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM13(...) rccDisableAPB1L(RCC_APB1LENR_TIM13EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM13 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM13() rccResetAPB1L(RCC_APB1LRSTR_TIM13RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM14 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM14(lp) rccEnableAPB1L(RCC_APB1LENR_TIM14EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM14 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM14(...) rccDisableAPB1L(RCC_APB1LENR_TIM14EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM14 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM14() rccResetAPB1L(RCC_APB1LRSTR_TIM14RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM15 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM15 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM15(...) rccDisableAPB2(RCC_APB2ENR_TIM15EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM15 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM16 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM16 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM16(...) rccDisableAPB2(RCC_APB2ENR_TIM16EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM16 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM17 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM17 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM17(...) rccDisableAPB2(RCC_APB2ENR_TIM17EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM17 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name USART/UART peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USART1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART1(...) rccDisableAPB2(RCC_APB2ENR_USART1EN)
|
|
|
|
/**
|
|
* @brief Resets the USART1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
|
|
|
|
/**
|
|
* @brief Enables the USART2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART2(lp) rccEnableAPB1L(RCC_APB1LENR_USART2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART2(...) rccDisableAPB1L(RCC_APB1LENR_USART2EN)
|
|
|
|
/**
|
|
* @brief Resets the USART2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART2() rccResetAPB1L(RCC_APB1LRSTR_USART2RST)
|
|
|
|
/**
|
|
* @brief Enables the USART3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART3(lp) rccEnableAPB1L(RCC_APB1LENR_USART3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART3(...) rccDisableAPB1L(RCC_APB1LENR_USART3EN)
|
|
|
|
/**
|
|
* @brief Resets the USART3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART3() rccResetAPB1L(RCC_APB1LRSTR_USART3RST)
|
|
|
|
/**
|
|
* @brief Enables the UART4 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART4(lp) rccEnableAPB1L(RCC_APB1LENR_UART4EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the UART4 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART4(...) rccDisableAPB1L(RCC_APB1LENR_UART4EN)
|
|
|
|
/**
|
|
* @brief Resets the UART4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART4() rccResetAPB1L(RCC_APB1LRSTR_UART4RST)
|
|
|
|
/**
|
|
* @brief Enables the UART5 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART5(lp) rccEnableAPB1L(RCC_APB1LENR_UART5EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the UART5 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART5(...) rccDisableAPB1L(RCC_APB1LENR_UART5EN)
|
|
|
|
/**
|
|
* @brief Resets the UART5 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART5() rccResetAPB1L(RCC_APB1LRSTR_UART5RST)
|
|
|
|
/**
|
|
* @brief Enables the USART6 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART6 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART6(...) rccDisableAPB2(RCC_APB2ENR_USART6EN)
|
|
|
|
/**
|
|
* @brief Resets the USART6 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
|
|
|
|
/**
|
|
* @brief Enables the UART7 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART7(lp) rccEnableAPB1L(RCC_APB1LENR_UART7EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the UART7 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART7(...) rccDisableAPB1L(RCC_APB1LENR_UART7EN)
|
|
|
|
/**
|
|
* @brief Resets the UART7 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART7() rccResetAPB1L(RCC_APB1LRSTR_UART7RST)
|
|
|
|
/**
|
|
* @brief Enables the UART8 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART8(lp) rccEnableAPB1L(RCC_APB1LENR_UART8EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the UART8 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART8(...) rccDisableAPB1L(RCC_APB1LENR_UART8EN)
|
|
|
|
/**
|
|
* @brief Resets the UART8 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART8() rccResetAPB1L(RCC_APB1LRSTR_UART8RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name LTDC peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the LTDC peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableLTDC(lp) rccEnableAPB3(RCC_APB3ENR_LTDCEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the LTDC peripheral clock.
|
|
. *
|
|
* @api
|
|
*/
|
|
#define rccDisableLTDC() rccDisableAPB3(RCC_APB3ENR_LTDCEN)
|
|
|
|
/**
|
|
* @brief Resets the LTDC peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetLTDC() rccResetAPB3(RCC_APB3RSTR_LTDCRST)
|
|
|
|
/**
|
|
* @name DMA2D peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the DMA2D peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableDMA2D(lp) rccEnableAHB3(RCC_AHB3ENR_DMA2DEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the DMA2D peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableDMA2D() rccDisableAHB3(RCC_AHB3ENR_DMA2DEN)
|
|
|
|
/**
|
|
* @brief Resets the DMA2D peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetDMA2D() rccResetAHB3(RCC_AHB3RSTR_DMA2DRST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name FSMC peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the FSMC peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#if defined(STM32_FSMC_IS_FMC)
|
|
#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
|
|
#else
|
|
#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Disables the FSMC peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#if defined(STM32_FSMC_IS_FMC)
|
|
#define rccDisableFSMC(...) rccDisableAHB3(RCC_AHB3ENR_FMCEN)
|
|
#else
|
|
#define rccDisableFSMC(...) rccDisableAHB3(RCC_AHB3ENR_FSMCEN)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Resets the FSMC peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#if defined(STM32_FSMC_IS_FMC)
|
|
#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
|
|
#else
|
|
#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
|
|
#endif
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _STM32_RCC_ */
|
|
|
|
/** @} */
|