327 lines
12 KiB
C
327 lines
12 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32L5xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 7...0 Lowest...Highest.
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* 3...0 Lowest...Highest (trusted mode).
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32L5xx_MCUCONF
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#define STM32L552_MCUCONF
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#define STM32L562_MCUCONF
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/*
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* HAL driver global settings.
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*/
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#define STM32_NO_INIT FALSE
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/*
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* ICache settings.
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*/
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#define STM32_ICACHE_CR (ICACHE_CR_EN)
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#define STM32_ICACHE_CRR0 0
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#define STM32_ICACHE_CRR1 0
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#define STM32_ICACHE_CRR2 0
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#define STM32_ICACHE_CRR3 0
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/*
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* Power settings.
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*/
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#define STM32_VOS STM32_VOS_RANGE0
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#define STM32_PWR_CR2 (PWR_CR2_IOSV | PWR_CR2_PLS_LEV0)
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#define STM32_PWR_CR3 (0U)
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#define STM32_PWR_CR4 (0U)
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/*
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* Clock settings.
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*/
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_MSIPLL_ENABLED TRUE
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#define STM32_MSIRANGE STM32_MSIRANGE_4M
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#define STM32_MSISRANGE STM32_MSISRANGE_4M
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_MSI
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#define STM32_PLLM_VALUE 1
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#define STM32_PLLN_VALUE 55
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#define STM32_PLLPDIV_VALUE 0
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#define STM32_PLLP_VALUE 7
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#define STM32_PLLQ_VALUE 4
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#define STM32_PLLR_VALUE 2
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#define STM32_PLLSAI1SRC STM32_PLLSAI1SRC_MSI
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#define STM32_PLLSAI1M_VALUE 1
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#define STM32_PLLSAI1N_VALUE 72
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#define STM32_PLLSAI1PDIV_VALUE 6
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#define STM32_PLLSAI1P_VALUE 7
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#define STM32_PLLSAI1Q_VALUE 6
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#define STM32_PLLSAI1R_VALUE 6
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#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
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#define STM32_PLLSAI2M_VALUE 1
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#define STM32_PLLSAI2N_VALUE 72
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#define STM32_PLLSAI2PDIV_VALUE 6
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#define STM32_PLLSAI2P_VALUE 7
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_STOPWUCK STM32_STOPWUCK_MSI
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clock sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
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#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
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#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
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#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
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#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
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#define STM32_FDCANSEL STM32_FDCANSEL_PLL
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#define STM32_CLK48SEL STM32_CLK48SEL_PLL
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_ADFSDMSEL STM32_ADFSDMSEL_SAI1CLK
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF
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#define STM32_SAI2SEL STM32_SAI2SEL_OFF
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#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
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#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 2
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#define STM32_IRQ_EXTI1_PRIORITY 2
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#define STM32_IRQ_EXTI2_PRIORITY 2
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#define STM32_IRQ_EXTI3_PRIORITY 2
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#define STM32_IRQ_EXTI4_PRIORITY 2
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#define STM32_IRQ_EXTI5_PRIORITY 2
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#define STM32_IRQ_EXTI6_PRIORITY 2
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#define STM32_IRQ_EXTI7_PRIORITY 2
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#define STM32_IRQ_EXTI8_PRIORITY 2
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#define STM32_IRQ_EXTI9_PRIORITY 2
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#define STM32_IRQ_EXTI10_PRIORITY 2
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#define STM32_IRQ_EXTI11_PRIORITY 2
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#define STM32_IRQ_EXTI12_PRIORITY 2
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#define STM32_IRQ_EXTI13_PRIORITY 2
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#define STM32_IRQ_EXTI14_PRIORITY 2
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#define STM32_IRQ_EXTI15_PRIORITY 2
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#define STM32_IRQ_EXTI1635_38_PRIORITY 2
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#define STM32_IRQ_EXTI17_PRIORITY 2
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#define STM32_IRQ_EXTI18_PRIORITY 2
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#define STM32_IRQ_EXTI19_PRIORITY 2
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#define STM32_IRQ_EXTI20_PRIORITY 2
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#define STM32_IRQ_EXTI21_22_PRIORITY 2
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#define STM32_IRQ_FDCAN1_PRIORITY 1
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#define STM32_IRQ_TIM1_BRK_PRIORITY 1
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#define STM32_IRQ_TIM1_UP_PRIORITY 1
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#define STM32_IRQ_TIM1_TRGCO_PRIORITY 1
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#define STM32_IRQ_TIM1_CC_PRIORITY 1
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#define STM32_IRQ_TIM2_PRIORITY 1
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#define STM32_IRQ_TIM3_PRIORITY 1
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#define STM32_IRQ_TIM4_PRIORITY 1
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#define STM32_IRQ_TIM5_PRIORITY 1
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#define STM32_IRQ_TIM6_PRIORITY 1
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#define STM32_IRQ_TIM7_PRIORITY 1
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#define STM32_IRQ_TIM8_UP_PRIORITY 1
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#define STM32_IRQ_TIM8_CC_PRIORITY 1
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#define STM32_IRQ_TIM15_PRIORITY 1
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#define STM32_IRQ_TIM16_PRIORITY 1
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#define STM32_IRQ_TIM17_PRIORITY 1
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#define STM32_IRQ_TIM20_UP_PRIORITY 1
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#define STM32_IRQ_TIM20_CC_PRIORITY 1
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#define STM32_IRQ_USART1_PRIORITY 1
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#define STM32_IRQ_USART2_PRIORITY 1
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#define STM32_IRQ_USART3_PRIORITY 1
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#define STM32_IRQ_UART4_PRIORITY 1
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#define STM32_IRQ_UART5_PRIORITY 1
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#define STM32_IRQ_LPUART1_PRIORITY 1
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/*
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* ADC driver system settings.
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*/
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/*
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* CAN driver system settings.
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*/
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/*
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* DAC driver system settings.
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*/
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM15 FALSE
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#define STM32_GPT_USE_TIM16 FALSE
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#define STM32_GPT_USE_TIM17 FALSE
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/*
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* I2C driver system settings.
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*/
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM15 FALSE
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#define STM32_ICU_USE_TIM16 FALSE
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#define STM32_ICU_USE_TIM17 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM8 FALSE
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#define STM32_PWM_USE_TIM15 FALSE
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#define STM32_PWM_USE_TIM16 FALSE
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#define STM32_PWM_USE_TIM17 FALSE
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#define STM32_PWM_USE_TIM20 FALSE
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/*
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* RTC driver system settings.
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*/
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/*
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* SDC driver system settings.
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*/
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USE_LPUART1 TRUE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 5
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#define STM32_SPI_SPI2_IRQ_PRIORITY 5
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#define STM32_SPI_SPI3_IRQ_PRIORITY 5
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 1
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#define STM32_ST_USE_TIMER 2
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/*
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* TRNG driver system settings.
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*/
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#define STM32_TRNG_USE_RNG1 FALSE
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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/*
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* WSPI driver system settings.
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*/
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#endif /* MCUCONF_H */
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