554 lines
17 KiB
C
554 lines
17 KiB
C
/*
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ChibiOS/NIL - Copyright (C) 2013,2014 Giovanni Di Sirio.
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This file is part of ChibiOS/NIL.
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ChibiOS/NIL is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/NIL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file chcore_v7m.h
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* @brief ARMv7-M architecture port macros and structures.
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*
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* @addtogroup ARMCMx_V7M_CORE
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* @{
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*/
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#ifndef _CHCORE_V7M_H_
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#define _CHCORE_V7M_H_
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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/**
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* @name Architecture and Compiler
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* @{
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*/
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#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
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/**
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* @brief Macro defining the specific ARM architecture.
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*/
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#define PORT_ARCHITECTURE_ARM_v7M
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/**
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* @brief Name of the implemented architecture.
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*/
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#define PORT_ARCHITECTURE_NAME "ARMv7-M"
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/**
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* @brief Name of the architecture variant.
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*/
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#define PORT_CORE_VARIANT_NAME "Cortex-M3"
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#elif (CORTEX_MODEL == CORTEX_M4)
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#define PORT_ARCHITECTURE_ARM_v7ME
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#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
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#if CORTEX_USE_FPU
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#define PORT_CORE_VARIANT_NAME "Cortex-M4F"
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#else
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#define PORT_CORE_VARIANT_NAME "Cortex-M4"
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#endif
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#endif
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/**
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* @brief Port-specific information string.
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*/
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#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
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#define PORT_INFO "Advanced kernel mode"
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#else
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#define PORT_INFO "Compact kernel mode"
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#endif
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/** @} */
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/**
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* @brief This port supports a realtime counter.
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*/
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#define PORT_SUPPORTS_RT FALSE //TRUE
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/**
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* @brief Disabled value for BASEPRI register.
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*/
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#define CORTEX_BASEPRI_DISABLED 0
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p PORT_INT_REQUIRED_STACK.
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* @note In this port it is set to 16 because the idle thread does have
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* a stack frame when compiling without optimizations. You may
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* reduce this value to zero when compiling with optimizations.
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*/
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#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
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#define PORT_IDLE_THREAD_STACK_SIZE 16
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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* @note In this port this value is conservatively set to 32 because the
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* function @p chSchDoReschedule() can have a stack frame, especially
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* with compiler optimizations disabled. The value can be reduced
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* when compiler optimizations are enabled.
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*/
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#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
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#define PORT_INT_REQUIRED_STACK 32
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#endif
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/**
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* @brief Enables the use of the WFI instruction in the idle thread loop.
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*/
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#if !defined(CORTEX_ENABLE_WFI_IDLE)
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#define CORTEX_ENABLE_WFI_IDLE FALSE
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#endif
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/**
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* @brief FPU support in context switch.
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* @details Activating this option activates the FPU support in the kernel.
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*/
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#if !defined(CORTEX_USE_FPU)
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#define CORTEX_USE_FPU CORTEX_HAS_FPU
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#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
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/* This setting requires an FPU presence check in case it is externally
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redefined.*/
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#error "the selected core does not have an FPU"
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#endif
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/**
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* @brief Simplified priority handling flag.
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* @details Activating this option makes the Kernel work in compact mode.
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* In compact mode interrupts are disabled globally instead of
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* raising the priority mask to some intermediate level.
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*/
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#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
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#define CORTEX_SIMPLIFIED_PRIORITY FALSE
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#endif
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/**
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* @brief SVCALL handler priority.
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* @note The default SVCALL handler priority is defaulted to
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* @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
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* @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
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* priority level.
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*/
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#if !defined(CORTEX_PRIORITY_SVCALL)
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#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
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#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
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/* If it is externally redefined then better perform a validity check on it.*/
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#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
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#endif
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/**
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* @brief NVIC VTOR initialization expression.
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*/
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#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
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#define CORTEX_VTOR_INIT 0x00000000
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#endif
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/**
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* @brief NVIC PRIGROUP initialization expression.
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* @details The default assigns all available priority bits as preemption
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* priority with no sub-priority.
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*/
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#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
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#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
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/**
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* @brief Maximum usable priority for normal ISRs.
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*/
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#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
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/**
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* @brief BASEPRI level within kernel lock.
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*/
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#define CORTEX_BASEPRI_KERNEL \
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CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
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#else
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#define CORTEX_MAX_KERNEL_PRIORITY 0
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#endif
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/**
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* @brief PendSV priority level.
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* @note This priority is enforced to be equal to
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* @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
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* highest priority that cannot preempt the kernel.
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*/
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#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
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/*===========================================================================*/
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/* Module data structures and types. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/* The documentation of the following declarations is in chconf.h in order
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to not have duplicated structure names into the documentation.*/
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#if !defined(__DOXYGEN__)
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struct port_extctx {
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t r12;
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regarm_t lr_thd;
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regarm_t pc;
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regarm_t xpsr;
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#if CORTEX_USE_FPU
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regarm_t s0;
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regarm_t s1;
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regarm_t s2;
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regarm_t s3;
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regarm_t s4;
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regarm_t s5;
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regarm_t s6;
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regarm_t s7;
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regarm_t s8;
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regarm_t s9;
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regarm_t s10;
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regarm_t s11;
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regarm_t s12;
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regarm_t s13;
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regarm_t s14;
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regarm_t s15;
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regarm_t fpscr;
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regarm_t reserved;
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#endif /* CORTEX_USE_FPU */
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};
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struct port_intctx {
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#if CORTEX_USE_FPU
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regarm_t s16;
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regarm_t s17;
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regarm_t s18;
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regarm_t s19;
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regarm_t s20;
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regarm_t s21;
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regarm_t s22;
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regarm_t s23;
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regarm_t s24;
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regarm_t s25;
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regarm_t s26;
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regarm_t s27;
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regarm_t s28;
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regarm_t s29;
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regarm_t s30;
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regarm_t s31;
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#endif /* CORTEX_USE_FPU */
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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};
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#endif /* !defined(__DOXYGEN__) */
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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/**
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* @brief Platform dependent thread stack setup.
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* @details This code usually setup the context switching frame represented
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* by an @p port_intctx structure.
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*/
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#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
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(tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) - \
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sizeof(struct port_intctx)); \
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(tp)->ctxp->r4 = (regarm_t)(pf); \
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(tp)->ctxp->r5 = (regarm_t)(arg); \
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(tp)->ctxp->lr = (regarm_t)(_port_thread_start); \
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}
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/**
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* @brief Computes the thread working area global size.
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* @note There is no need to perform alignments in this macro.
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*/
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#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
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sizeof(struct port_extctx) + \
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(n) + (PORT_INT_REQUIRED_STACK))
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/**
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* @brief IRQ prologue code.
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* @details This macro must be inserted at the start of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE()
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/**
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* @brief IRQ epilogue code.
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* @details This macro must be inserted at the end of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
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/**
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* @brief IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_IRQ_HANDLER(id) void id(void)
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/**
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* @brief Fast IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_FAST_IRQ_HANDLER(id) void id(void)
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/**
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* @brief Performs a context switch between two threads.
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* @details This is the most critical code in any port, this function
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* is responsible for the context switch between 2 threads.
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* @note The implementation of this code affects <b>directly</b> the context
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* switch performance so optimize here as much as you can.
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*
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* @param[in] ntp the thread to be switched in
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* @param[in] otp the thread to be switched out
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*/
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#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
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#define port_switch(ntp, otp) _port_switch(ntp, otp)
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#else
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#define port_switch(ntp, otp) { \
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struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
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if ((stkalign_t *)(r13 - 1) < (otp)->stklim) \
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chSysHalt("stack overflow"); \
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_port_switch(ntp, otp); \
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}
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#endif
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void _port_irq_epilogue(void);
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void _port_switch(thread_t *ntp, thread_t *otp);
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void _port_thread_start(void);
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void _port_switch_from_isr(void);
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void _port_exit_from_isr(void);
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#ifdef __cplusplus
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}
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#endif
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/*===========================================================================*/
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/* Module inline functions. */
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/*===========================================================================*/
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/**
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* @brief Port-related initialization code.
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*/
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static inline void port_init(void) {
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/* Initialization of the vector table and priority related settings.*/
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SCB->VTOR = CORTEX_VTOR_INIT;
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/* Initializing priority grouping.*/
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NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
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/* DWT cycle counter enable.*/
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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/* Initialization of the system vectors used by the port.*/
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#if !CORTEX_SIMPLIFIED_PRIORITY
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NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
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#endif
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NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
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}
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/**
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* @brief Returns a word encoding the current interrupts status.
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*
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* @return The interrupts status.
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*/
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static inline syssts_t port_get_irq_status(void) {
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register uint32_t sts;
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#if !CORTEX_SIMPLIFIED_PRIORITY
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sts = __get_BASEPRI();
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#else /* CORTEX_SIMPLIFIED_PRIORITY */
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sts = __get_PRIMASK();
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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return sts;
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}
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/**
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* @brief Checks the interrupt status.
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*
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* @param[in] sts the interrupt status word
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*
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* @return The interrupt status.
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* @retvel false the word specified a disabled interrupts status.
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* @retvel true the word specified an enabled interrupts status.
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*/
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static inline bool port_irq_enabled(syssts_t sts) {
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#if !CORTEX_SIMPLIFIED_PRIORITY
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return sts == CORTEX_BASEPRI_DISABLED;
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#else /* CORTEX_SIMPLIFIED_PRIORITY */
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return (sts & 1) == 0;
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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}
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/**
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* @brief Determines the current execution context.
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*
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* @return The execution context.
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* @retval false not running in ISR mode.
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* @retval true running in ISR mode.
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*/
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static inline bool port_is_isr_context(void) {
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return (bool)((__get_IPSR() & 0x1FF) != 0);
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}
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/**
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* @brief Kernel-lock action.
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* @details In this port this function raises the base priority to kernel
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* level.
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*/
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static inline void port_lock(void) {
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#if !CORTEX_SIMPLIFIED_PRIORITY
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__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
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#else /* CORTEX_SIMPLIFIED_PRIORITY */
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__disable_irq();
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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}
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/**
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* @brief Kernel-unlock action.
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* @details In this port this function lowers the base priority to user
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* level.
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*/
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static inline void port_unlock(void) {
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#if !CORTEX_SIMPLIFIED_PRIORITY
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__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
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#else /* CORTEX_SIMPLIFIED_PRIORITY */
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__enable_irq();
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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}
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/**
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* @brief Kernel-lock action from an interrupt handler.
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* @details In this port this function raises the base priority to kernel
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* level.
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* @note Same as @p port_lock() in this port.
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*/
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static inline void port_lock_from_isr(void) {
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port_lock();
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}
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/**
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* @brief Kernel-unlock action from an interrupt handler.
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* @details In this port this function lowers the base priority to user
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* level.
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* @note Same as @p port_unlock() in this port.
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*/
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static inline void port_unlock_from_isr(void) {
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port_unlock();
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}
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/**
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* @brief Disables all the interrupt sources.
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* @note In this port it disables all the interrupt sources by raising
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* the priority mask to level 0.
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*/
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static inline void port_disable(void) {
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__disable_irq();
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}
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/**
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* @brief Disables the interrupt sources below kernel-level priority.
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* @note Interrupt sources above kernel level remains enabled.
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* @note In this port it raises/lowers the base priority to kernel level.
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*/
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static inline void port_suspend(void) {
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#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
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__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
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__enable_irq();
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#else
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__disable_irq();
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#endif
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}
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/**
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* @brief Enables all the interrupt sources.
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* @note In this port it lowers the base priority to user level.
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*/
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static inline void port_enable(void) {
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#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
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__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
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#endif
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__enable_irq();
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}
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/**
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* @brief Enters an architecture-dependent IRQ-waiting mode.
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* @details The function is meant to return when an interrupt becomes pending.
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|
* The simplest implementation is an empty function or macro but this
|
|
* would not take advantage of architecture-specific power saving
|
|
* modes.
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|
* @note Implemented as an inlined @p WFI instruction.
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|
*/
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|
static inline void port_wait_for_interrupt(void) {
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|
|
|
#if CORTEX_ENABLE_WFI_IDLE
|
|
__WFI;
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the current value of the realtime counter.
|
|
*
|
|
* @return The realtime counter value.
|
|
*/
|
|
static inline rtcnt_t port_rt_get_counter_value(void) {
|
|
|
|
return DWT->CYCCNT;
|
|
}
|
|
|
|
#endif /* !defined(_FROM_ASM_) */
|
|
|
|
#endif /* _CHCORE_V7M_H_ */
|
|
|
|
/** @} */
|