148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#undef FALSE
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#undef TRUE
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#ifndef __STM32F10x_MAP_H
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#include "stm32lib/stm32f10x_map.h"
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#endif
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#define BOARD_OLIMEX_STM32_P103
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/*
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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*/
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//#define SYSCLK_48
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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*/
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#define LSECLK 32768
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#define HSECLK 8000000
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#define HSICLK 8000000
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#define PLLPRE 1
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#ifdef SYSCLK_48
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#define PLLMUL 6
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#else
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#define PLLMUL 9
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#ifdef SYSCLK_48
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#define USBPREBITS USBPRE_DIV1_BITS
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#define FLASHBITS 0x00000011
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#else
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#define USBPREBITS USBPRE_DIV1P5_BITS
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#define FLASHBITS 0x00000012
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#endif
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/*
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* Definitions for RCC_CR register.
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*/
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#define CR_HSION_MASK (0x1 << 0)
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#define CR_HSIRDY_MASK (0x1 << 1)
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#define CR_HSITRIM_MASK (0x1F << 3)
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#define HSITRIM_RESET_BITS (1 << 3)
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#define CR_HSICAL_MASK (0xFF << 8)
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#define CR_HSEON_MASK (0x1 << 16)
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#define CR_HSERDY_MASK (0x1 << 17)
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#define CR_HSEBYP_MASK (0x1 << 18)
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#define CR_CSSON_MASK (0x1 << 19)
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#define CR_PLLON_MASK (0x1 << 24)
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#define CR_PLLRDY_MASK (0x1 << 25)
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/*
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* Definitions for RCC_CFGR register.
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*/
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#define CFGR_SW_MASK (0x3 << 0)
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#define SW_HSI_BITS (0 << 0)
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#define SW_HSE_BITS (1 << 0)
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#define SW_PLL_BITS (2 << 0)
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#define CFGR_SWS_MASK (0x3 << 2)
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#define SWS_HSI_BITS (0 << 2)
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#define SWS_HSE_BITS (1 << 2)
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#define SWS_PLL_BITS (2 << 2)
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#define CFGR_HPRE_MASK (0xF << 4)
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#define HPRE_DIV1_BITS (0 << 4)
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#define CFGR_PPRE1_MASK (0x7 << 8)
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#define PPRE1_DIV1_BITS (0 << 8)
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#define PPRE1_DIV2_BITS (4 << 8)
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#define CFGR_PPRE2_MASK (0x7 << 11)
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#define PPRE2_DIV1_BITS (0 << 11)
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#define PPRE2_DIV2_BITS (4 << 11)
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#define CFGR_ADCPRE_MASK (0x3 << 14)
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#define ADCPRE_DIV2_BITS (0 << 14)
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#define ADCPRE_DIV4_BITS (1 << 14)
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#define ADCPRE_DIV6_BITS (2 << 14)
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#define ADCPRE_DIV8_BITS (3 << 14)
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#define CFGR_PLLSRC_MASK (0x1 << 16)
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#define PLLSRC_HSI_BITS (0 << 16)
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#define PLLSRC_HSE_BITS (1 << 16)
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#define CFGR_PLLXTPRE_MASK (0x1 << 17)
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#define CFGR_PLLMUL_MASK (0xF << 18)
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#define CFGR_USBPRE_MASK (0x1 << 22)
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#define USBPRE_DIV1P5_BITS (0 << 22)
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#define USBPRE_DIV1_BITS (1 << 22)
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#define CFGR_MCO_MASK (0x7 << 24)
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#define MCO_DISABLED_BITS (0 << 24)
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/*
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* IO pins assignments.
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*/
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#define GPIOA_BUTTON (1 << 0)
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#define GPIOC_MMCWP (1 << 6)
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#define GPIOC_MMCCP (1 << 7)
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#define GPIOC_CANCNTL (1 << 10)
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#define GPIOC_DISC (1 << 11)
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#define GPIOC_LED (1 << 12)
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/*
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* All inputs with pullups unless otherwise specified.
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*/
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#define VAL_GPIOACRL 0x88888884 // PA0:FI
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#define VAL_GPIOACRH 0x88888888
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#define VAL_GPIOAODR 0xFFFFFFFF
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#define VAL_GPIOBCRL 0x88883888 // PB3:PP
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#define VAL_GPIOBCRH 0x88888888
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#define VAL_GPIOBODR 0xFFFFFFFF
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#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI
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#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP
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#define VAL_GPIOCODR 0xFFFFFFFF
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#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI
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#define VAL_GPIODCRH 0x88888888
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#define VAL_GPIODODR 0xFFFFFFFF
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#endif /* _BOARD_H_ */
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