532 lines
22 KiB
C
532 lines
22 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/hal_lld_f105_f107.h
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* @brief STM32F10x Connectivity Line HAL subsystem low level driver header.
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*
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* @addtogroup STM32F10X_CL_HAL
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* @{
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*/
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#ifndef _HAL_LLD_F105_F107_H_
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#define _HAL_LLD_F105_F107_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define STM32_HSICLK 8000000 /**< High speed internal clock. */
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#define STM32_LSICLK 40000 /**< Low speed internal clock. */
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/* RCC_CFGR register bits definitions.*/
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#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
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#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
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#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
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#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is
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PREDIV1. */
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#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */
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#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */
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#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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#define STM32_MCO_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
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#define STM32_MCO_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
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#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
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#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
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/* RCC_CFGR2 register bits definitions.*/
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#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
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#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
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/*===========================================================================*/
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/* Platform specific friendly IRQ names. */
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/*===========================================================================*/
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#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
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#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
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detect. */
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#define TAMPER_IRQHandler Vector48 /**< Tamper. */
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#define RTC_IRQHandler Vector4C /**< RTC. */
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#define FLASH_IRQHandler Vector50 /**< Flash. */
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#define RCC_IRQHandler Vector54 /**< RCC. */
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#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
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#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
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#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
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#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
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#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
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#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
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#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
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#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
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#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
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#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
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#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
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#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
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#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */
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#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
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#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
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#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
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#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
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#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
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#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
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#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
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#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
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Commutation. */
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#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
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#define TIM2_IRQHandler VectorB0 /**< TIM2. */
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#define TIM3_IRQHandler VectorB4 /**< TIM3. */
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#define TIM4_IRQHandler VectorB8 /**< TIM4. */
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#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
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#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
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#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
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#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */
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#define SPI1_IRQHandler VectorCC /**< SPI1. */
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#define SPI2_IRQHandler VectorD0 /**< SPI2. */
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#define USART1_IRQHandler VectorD4 /**< USART1. */
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#define USART2_IRQHandler VectorD8 /**< USART2. */
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#define USART3_IRQHandler VectorDC /**< USART3. */
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#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
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#define RTCAlarm_IRQHandler VectorE4 /**< RTC alarm through EXTI
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line. */
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#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through
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EXTI line. */
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#define TIM5_IRQHandler Vector108 /**< TIM5. */
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#define SPI3_IRQHandler Vector10C /**< SPI3. */
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#define UART4_IRQHandler Vector110 /**< UART4. */
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#define UART5_IRQHandler Vector114 /**< UART5. */
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#define TIM6_IRQHandler Vector118 /**< TIM6. */
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#define TIM7_IRQHandler Vector11C /**< TIM7. */
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#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */
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#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */
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#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */
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#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */
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#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */
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#define ETH_IRQHandler Vector134 /**< Ethernet. */
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#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through
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EXTI line. */
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#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */
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#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */
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#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */
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#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */
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#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_SW) || defined(__DOXYGEN__)
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#define STM32_SW STM32_SW_PLL
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#endif
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/**
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_PREDIV1
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#endif
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/**
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* @brief PREDIV1 clock source.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__)
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#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2
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#endif
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/**
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* @brief PREDIV1 division factor.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The allowed range is 1...16.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__)
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#define STM32_PREDIV1_VALUE 5
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#endif
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/**
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* @brief PLL multiplier value.
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* @note The allowed range is 4...9.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLMUL_VALUE 9
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#endif
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/**
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* @brief PREDIV2 division factor.
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* @note This setting has only effect if the PLL2 is selected as the
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* clock source for the PLL.
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* @note The allowed range is 1...16.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__)
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#define STM32_PREDIV2_VALUE 5
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#endif
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/**
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* @brief PLL2 multiplier value.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL2MUL_VALUE 8
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#endif
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 72MHz system clock from
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* a 25MHz crystal using both PLL and PLL2.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_HPRE STM32_HPRE_DIV1
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#endif
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/**
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* @brief APB1 prescaler value.
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*/
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#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#endif
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/**
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* @brief APB2 prescaler value.
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*/
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#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#endif
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/**
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* @brief ADC prescaler value.
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*/
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#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#endif
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/**
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* @brief MCO pin setting.
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*/
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#if !defined(STM32_MCO) || defined(__DOXYGEN__)
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#define STM32_MCO STM32_MCO_NOCLOCK
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @brief PREDIV1 field.
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*/
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#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) || \
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defined(__DOXYGEN__)
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#define STM32_PREDIV1 ((STM32_PREDIV1_VALUE - 1) << 0)
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#else
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#error "invalid STM32_PREDIV1_VALUE value specified"
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#endif
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/**
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* @brief PREDIV2 field.
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*/
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#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) || \
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defined(__DOXYGEN__)
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#define STM32_PREDIV2 ((STM32_PREDIV2_VALUE - 1) << 4)
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#else
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#error "invalid STM32_PREDIV2_VALUE value specified"
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#endif
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/**
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* @brief PLLMUL field.
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*/
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#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#else
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#error "invalid STM32_PLLMUL_VALUE value specified"
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#endif
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/**
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* @brief PLL2MUL field.
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*/
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#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) || \
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defined(__DOXYGEN__)
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#define STM32_PLL2MUL ((STM32_PLLMUL_VALUE - 2) << 8)
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#elif (STM32_PLL2MUL_VALUE == 16)
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#define STM32_PLL2MUL (14 << 8)
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#elif (STM32_PLL2MUL_VALUE == 20)
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#define STM32_PLL2MUL (15 << 8)
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#else
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#error "invalid STM32_PLL2MUL_VALUE value specified"
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#endif
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/* The following values are only used if PLL2 clock is selected as source
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for the PLL clock */
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#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
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/**
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* @brief PLL2 input frequency.
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*/
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#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE)
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/* PLL2 input frequency range check.*/
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#if (STM32_PLL2CLKIN < 3000000) || (STM32_PLL2CLKIN > 5000000)
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#error "STM32_PLL2CLKIN outside acceptable range (3...5MHz)"
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#endif
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/**
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* @brief PLL2 output clock frequency.
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*/
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#define STM32_PLL2CLKOUT (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
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/* PLL2 output frequency range check.*/
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#if (STM32_PLL2CLKOUT < 40000000) || (STM32_PLL2CLKOUT > 74000000)
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#error "STM32_PLL2CLKOUT outside acceptable range (40...74MHz)"
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#endif
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#endif /* STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 */
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/**
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* @brief PREDIV1 input frequency.
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*/
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#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
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#define STM32_PREDIV1CLK STM32_PLL2CLKOUT
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#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE
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#define STM32_PREDIV1CLK STM32_HSECLK
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#else
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#error "invalid STM32_PREDIV1SRC value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
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#define STM32_PLLCLKIN (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/* PLL input frequency range check.*/
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#if (STM32_PLLCLKIN < 3000000) || (STM32_PLLCLKIN > 12000000)
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#error "STM32_PLLCLKIN outside acceptable range (3...12MHz)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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/* PLL output frequency range check.*/
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#if (STM32_PLLCLKOUT < 18000000) || (STM32_PLLCLKOUT > 72000000)
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#error "STM32_PLLCLKOUT outside acceptable range (18...72MHz)"
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#endif
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/**
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* @brief System clock source.
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*/
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#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#elif (STM32_SW == STM32_SW_HSI)
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#define STM32_SYSCLK STM32_HSICLK
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#elif (STM32_SW == STM32_SW_HSE)
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#define STM32_SYSCLK STM32_HSECLK
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#else
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#error "invalid STM32_SYSCLK_SW value specified"
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#endif
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/* Check on the system clock.*/
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#if STM32_SYSCLK > 72000000
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#error "STM32_SYSCLK above maximum rated frequency (72MHz)"
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#endif
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/**
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* @brief AHB frequency.
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*/
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#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#elif STM32_HPRE == STM32_HPRE_DIV2
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#define STM32_HCLK (STM32_SYSCLK / 2)
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#elif STM32_HPRE == STM32_HPRE_DIV4
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#define STM32_HCLK (STM32_SYSCLK / 4)
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#elif STM32_HPRE == STM32_HPRE_DIV8
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#define STM32_HCLK (STM32_SYSCLK / 8)
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#elif STM32_HPRE == STM32_HPRE_DIV16
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#define STM32_HCLK (STM32_SYSCLK / 16)
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#elif STM32_HPRE == STM32_HPRE_DIV64
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#define STM32_HCLK (STM32_SYSCLK / 64)
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#elif STM32_HPRE == STM32_HPRE_DIV128
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#define STM32_HCLK (STM32_SYSCLK / 128)
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#elif STM32_HPRE == STM32_HPRE_DIV256
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#define STM32_HCLK (STM32_SYSCLK / 256)
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#elif STM32_HPRE == STM32_HPRE_DIV512
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#define STM32_HCLK (STM32_SYSCLK / 512)
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#else
|
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#error "invalid STM32_HPRE value specified"
|
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#endif
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|
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/* AHB frequency check.*/
|
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#if STM32_HPRE > 72000000
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|
#error "STM32_HPRE exceeding maximum frequency (72MHz)"
|
|
#endif
|
|
|
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/**
|
|
* @brief APB1 frequency.
|
|
*/
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#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_PCLK1 (STM32_HCLK / 1)
|
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#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
|
#define STM32_PCLK1 (STM32_HCLK / 2)
|
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#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
|
#define STM32_PCLK1 (STM32_HCLK / 4)
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
|
#define STM32_PCLK1 (STM32_HCLK / 8)
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
|
#define STM32_PCLK1 (STM32_HCLK / 16)
|
|
#else
|
|
#error "invalid STM32_PPRE1 value specified"
|
|
#endif
|
|
|
|
/* APB1 frequency check.*/
|
|
#if STM32_PCLK1 > 36000000
|
|
#error "STM32_PCLK1 exceeding maximum frequency (36MHz)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief APB2 frequency.
|
|
*/
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_PCLK2 (STM32_HCLK / 1)
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
|
#define STM32_PCLK2 (STM32_HCLK / 2)
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
|
#define STM32_PCLK2 (STM32_HCLK / 4)
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
|
#define STM32_PCLK2 (STM32_HCLK / 8)
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
|
#define STM32_PCLK2 (STM32_HCLK / 16)
|
|
#else
|
|
#error "invalid STM32_PPRE2 value specified"
|
|
#endif
|
|
|
|
/* APB2 frequency check.*/
|
|
#if STM32_PCLK2 > 72000000
|
|
#error "STM32_PCLK2 exceeding maximum frequency (72MHz)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief ADC frequency.
|
|
*/
|
|
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
|
#else
|
|
#error "invalid STM32_ADCPRE value specified"
|
|
#endif
|
|
|
|
/* ADC frequency check.*/
|
|
#if STM32_ADCCLK > 14000000
|
|
#error "STM32_ADCCLK exceeding maximum frequency (14MHz)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief Timers 2, 3, 4, 5, 6, 7 clock.
|
|
*/
|
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
|
#else
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Timer 1 clock.
|
|
*/
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
|
#else
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Flash settings.
|
|
*/
|
|
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
|
#define STM32_FLASHBITS 0x00000010
|
|
#elif STM32_HCLK <= 48000000
|
|
#define STM32_FLASHBITS 0x00000011
|
|
#else
|
|
#define STM32_FLASHBITS 0x00000012
|
|
#endif
|
|
|
|
#endif /* _HAL_LLD_F105_F107_H_ */
|
|
|
|
/** @} */
|