233 lines
8.7 KiB
C
233 lines
8.7 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32H5xx/stm32_registry.h
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* @brief STM32H5xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef STM32_REGISTRY_H
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#define STM32_REGISTRY_H
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32H5xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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/* DAC attributes.*/
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#define STM32_DAC_HAS_MCR TRUE
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/* RCC attributes.*/
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#define STM32_RCC_HAS_LSI TRUE
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#define STM32_RCC_HAS_LSI_PRESCALER FALSE
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#define STM32_RCC_HAS_CSI TRUE
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#define STM32_RCC_HAS_HSI48 TRUE
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#define STM32_RCC_HAS_HSI TRUE
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#define STM32_RCC_HAS_LSE TRUE
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#define STM32_RCC_HAS_HSE TRUE
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#define STM32_RCC_HAS_PLL1 TRUE
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#define STM32_RCC_PLL1_HAS_P TRUE
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#define STM32_RCC_PLL1_HAS_Q TRUE
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#define STM32_RCC_PLL1_HAS_R TRUE
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#define STM32_RCC_HAS_PLL2 TRUE
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#define STM32_RCC_PLL2_HAS_P TRUE
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#define STM32_RCC_PLL2_HAS_Q TRUE
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#define STM32_RCC_PLL2_HAS_R TRUE
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#define STM32_RCC_HAS_PLL3 TRUE
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#define STM32_RCC_PLL3_HAS_P TRUE
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#define STM32_RCC_PLL3_HAS_Q TRUE
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#define STM32_RCC_PLL3_HAS_R TRUE
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/*===========================================================================*/
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/* STM32H562xx, STM32H563xx, STM32H573xx. */
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/*===========================================================================*/
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#if defined(STM32H562xx) || defined(STM32H563xx) || \
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defined(STM32H573xx) || defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_ADC5 FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_HAS_CR TRUE
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#define STM32_EXTI_SEPARATE_RF TRUE
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#define STM32_EXTI_NUM_LINES 58
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#define STM32_EXTI_IMR1_MASK 0xFFFE0000U
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#define STM32_EXTI_IMR2_MASK 0x03DBBFFFU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN | \
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RCC_AHB2ENR_GPIODEN | \
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RCC_AHB2ENR_GPIOEEN | \
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RCC_AHB2ENR_GPIOFEN | \
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RCC_AHB2ENR_GPIOGEN | \
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RCC_AHB2ENR_GPIOHEN | \
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RCC_AHB2ENR_GPIOIEN)
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 TRUE
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#define STM32_HAS_SDMMC2 TRUE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 1
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 TRUE
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#define STM32_HAS_UART7 TRUE
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#define STM32_HAS_UART8 TRUE
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#define STM32_HAS_UART9 TRUE
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#define STM32_HAS_USART10 TRUE
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#define STM32_HAS_USART11 TRUE
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#define STM32_HAS_UART12 TRUE
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
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#define STM32_USB_PMA_SIZE 2048
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#define STM32_USB_HAS_BCDR TRUE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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#endif /* defined(STM32H562xx) || defined(STM32H563xx) || defined(STM32H573xx) */
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/** @} */
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#endif /* STM32_REGISTRY_H */
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/** @} */
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