195 lines
4.8 KiB
INI
195 lines
4.8 KiB
INI
[Main]
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Signature=UDE_TARGINFO_2.0
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Description=STM XPC564A Mini Module with SPC564A70 (Jtag)
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Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash
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Description2=PLL set for 120MHz
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Description3=FLASH programming prepared but not enabled
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Description4=Write Filter for BAM Module
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MCUs=Controller0
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Architecture=PowerPC
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Vendor=STM
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Board=XPC564A Mini Module
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[Controller0]
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Family=PowerPC
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Type=SPC564A70
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Enabled=1
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IntClock=120000
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MemDevs=BAMWriteFilter
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ExtClock=8000
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[Controller0.Core]
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Protocol=PPCJTAG
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Enabled=1
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[Controller0.Core.LoadedAddOn]
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UDEMemtool=1
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[Controller0.Core.PpcJtagTargIntf]
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PortType=FTDI
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ResetWaitTime=50
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MaxJtagClk=5000
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DoSramInit=1
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UseNexus=1
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AdaptiveJtagPhaseShift=1
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ConnOption=Default
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ChangeJtagClk=-1
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HaltAfterReset=1
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SimioAddr=g_JtagSimioAccess
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FreezeTimers=1
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InvalidTlbOnReset=1
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InvalidateCache=1
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ForceCacheFlush=1
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IgnoreLockedLines=0
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ExecInitCmds=1
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JtagTapNumber=0
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JtagNumOfTaps=1
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JtagNumIrBefore=0
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JtagNumIrAfter=0
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SimioAddr=g_JtagSimioAccess
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FlushCache=0
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AllowMmuSetup=1
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UseExtReset=1
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HandleWdtBug=0
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ForceEndOfReset=0
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JtagViaPod=0
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AllowResetOnCheck=0
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ChangeMsr=0
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ChangeMsrValue=0x0
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ExecOnStartCmds=0
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ExecOnHaltCmds=0
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EnableProgramTimeMeasurement=0
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UseHwResetMode=0
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TargetPort=Default
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HandleNexusAccessBug=0
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CommDevSel=PortType=USB,Type=FTDI
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DoNotEnableTrapSwBrp=0
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BootPasswd0=0xFEEDFACE
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BootPasswd1=0xCAFEBEEF
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BootPasswd2=0xFFFFFFFF
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BootPasswd3=0xFFFFFFFF
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BootPasswd4=0xFFFFFFFF
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BootPasswd5=0xFFFFFFFF
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BootPasswd6=0xFFFFFFFF
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BootPasswd7=0xFFFFFFFF
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JtagIoType=Jtag
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ExecOnHaltCmdsWhileHalted=0
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TimerForPTM=Default
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AllowBreakOnUpdateBreakpoints=0
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ClearDebugStatusOnHalt=1
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HwResetMode=Simulate
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UseMasterNexusIfResetState=1
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UseLocalAddressTranslation=1
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Use64BitNexus=0
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InitSramOnlyWhenNotInitialized=0
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AllowHarrForUpdateDebugRegs=0
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DisableE2EECC=0
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UseCore0ForNexusMemoryAccessWhileRunning=0
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[Controller0.Core.PpcJtagTargIntf.InitScript]
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// select TLB 1
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SETSPR 0x274 0x10000108 0xFFFFFFFF
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// programm peripheral B modules
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// TLB 1, entry 0
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SETSPR 0x270 0x10000000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=1MB
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SETSPR 0x271 0xC0000500 0xFFFFFFFF
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// effective page number FFF00000, I,G
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SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
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// real page FFF00000, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm internal Flash, no cache because of flash
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// TLB 1, entry 1
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SETSPR 0x270 0x10010000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=16MB
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SETSPR 0x271 0xC0000700 0xFFFFFFFF
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// effective page number 00000000
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SETSPR 0x272 0x28 0xFFFFFFFF
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// real page 00000000, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0x3F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm external memory
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// TLB 1, entry 2
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SETSPR 0x270 0x10020000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=16MB
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SETSPR 0x271 0xC0000700 0xFFFFFFFF
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// effective page number 20000000
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SETSPR 0x272 0x20000020 0xFFFFFFFF
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// real page 20000000, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0x2000003F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm internal SRAM
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// TLB 1, entry 3
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SETSPR 0x270 0x10030000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=256k
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SETSPR 0x271 0xC0000400 0xFFFFFFFF
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// effective page number 40000000, I
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SETSPR 0x272 0x40000028 0xFFFFFFFF
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// real page 0x40000028, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0x4000003F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// programm peripheral A modules
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// TLB 1, entry 4
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SETSPR 0x270 0x10040000 0xFFFFFFFF
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// Valid, protect against invalidation, global entry, size=1MB
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SETSPR 0x271 0xC0000500 0xFFFFFFFF
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// effective page number C3F00000, I
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SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
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// real page C3F00000, UX,SX,UW,SW,UR,SR
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SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
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// execute TLB write instruction
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EXECOPCODE 0x7C0007A4
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// cache invalidate
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SETSPR 0x3F3 0x00000003 0x00000003
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SETSPR 0x3F3 0x00000000 0x00000003
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// setup IVOPR
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// points to internal memory at 0x40000000
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SETSPR 0x3F 0x40000000 0xFFFFFFFF
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// disable watchdog
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SET SWT_SR 0x0000C520
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SET SWT_SR 0x0000D928
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SET SWT_MCR 0xFF00000A
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// setup clock to 120MHz
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SET 0xC3F80008 0xF000003C 0xF00F00FF
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WAIT 0x2
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SET 0xC3F8000C 0x00000001 0x000000FF
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WAIT 0x5
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[Controller0.Core.PpcJtagTargIntf.OnStartScript]
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[Controller0.Core.PpcJtagTargIntf.OnHaltScript]
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[Controller0.BAMWriteFilter]
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Description=BAM WriteAccess Filter
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Range0Start=0xFFFFC000
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Range0Size=0x4000
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Enabled=1
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Handler=AccessFilter
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Mode=ReadOnly
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[Controller0.PFLASH]
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Enabled=1
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EnableMemtoolByDefault=1
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[Controller0.Core.DebugServer.DbgFramework]
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FRAMEWORK_COLOR=14804223
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[Controller0.EngineA.DebugServer.DbgFramework]
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FRAMEWORK_COLOR=14794944
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