463 lines
13 KiB
C
463 lines
13 KiB
C
/**
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* @file STM32/i2c_lld.c
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* @brief STM32 I2C subsystem low level driver source. Slave mode not implemented.
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* @addtogroup STM32_I2C
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#include "i2c_lld.h"
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief I2C1 driver identifier.*/
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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I2CDriver I2CD1;
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#endif
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/** @brief I2C2 driver identifier.*/
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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I2CDriver I2CD2;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief TODO: Status bits translation.
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*
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* @param[in] sr USART SR register value
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*
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* @return The error flags.
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*/
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static i2cflags_t translate_i2c_errors(uint16_t sr) {
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i2cflags_t sts = 0;
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if (sr & USART_SR_ORE)
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sts |= UART_OVERRUN_ERROR;
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if (sr & USART_SR_PE)
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sts |= UART_PARITY_ERROR;
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if (sr & USART_SR_FE)
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sts |= UART_FRAMING_ERROR;
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if (sr & USART_SR_NE)
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sts |= UART_NOISE_ERROR;
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if (sr & USART_SR_LBD)
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sts |= UART_BREAK_DETECTED;
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return sts;
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}
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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// TODO:remove this stub and write normal handler
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// this is simply trap for errors
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while TRUE{
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translate_i2c_errors(i2cp->id_i2c->SR1);
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}
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}
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/* This function handle all regular interrupt conditions
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* TODO: 10 bit address handling here
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*/
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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int i = 0;
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int n = 0;
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int m = 0;
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if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
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//i = i2cp->id_i2c->SR1;
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i2cp->id_state = I2C_MACTIVE;
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i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) |
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i2cp->id_slave_config->rw_bit; // write slave address in DR
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return;
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}
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// now "wait" interrupt with ADDR flag
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if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address successfully sent
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if(i2cp->id_i2c->SR2 & I2C_SR2_TRA){
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i2c_lld_txbyte(i2cp); // send first byte
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i2cp->id_state = I2C_MTRANSMIT; // change state
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return;
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}
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else {
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/* In order to generate the non-acknowledge pulse after the last received
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* data byte, the ACK bit must be cleared just after reading the second
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* last data byte (after second last RxNE event).
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*/
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if (i2cp->id_slave_config->rxbytes > 1)
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i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // set ACK bit
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i2cp->id_state = I2C_MRECEIVE; // change status
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return;
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}
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}
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// transmitting bytes one by one
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if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte written
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return;
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}
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//receiving bytes one by one
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if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
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// i = i2cp->id_i2c->SR1;
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// n = i2cp->id_i2c->SR2;
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if (i2c_lld_rxbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte read
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// i = i2cp->id_i2c->SR1;
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// n = i2cp->id_i2c->SR2;
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return;
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}
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// "wait" BTF bit in status register
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// if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
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if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE | I2C_SR1_BTF | I2C_SR1_TXE)){
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chSysLockFromIsr();
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i2cp->id_slave_config->id_callback(i2cp, i2cp->id_slave_config);
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i = i2cp->id_i2c->SR1;
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n = i2cp->id_i2c->SR2;
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m = i2cp->id_i2c->CR1;
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chSysUnlockFromIsr();
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return;
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}
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else{ // trap
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i = i2cp->id_i2c->SR1;
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n = i2cp->id_i2c->SR2;
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m = i2cp->id_i2c->CR1;
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return;
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}
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}
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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/**
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* @brief I2C1 event interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorBC) {
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CH_IRQ_PROLOGUE();
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i2c_serve_event_interrupt(&I2CD1);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief I2C1 error interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorC0) {
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CH_IRQ_PROLOGUE();
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i2c_serve_error_interrupt(&I2CD1);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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/**
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* @brief I2C2 event interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorC4) {
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CH_IRQ_PROLOGUE();
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i2c_serve_event_interrupt(&I2CD2);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief I2C2 error interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorC8) {
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CH_IRQ_PROLOGUE();
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i2c_serve_error_interrupt(&I2CD2);
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CH_IRQ_EPILOGUE();
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}
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#endif
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/**
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* @brief Low level I2C driver initialization.
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*/
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void i2c_lld_init(void) {
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#if STM32_I2C_USE_I2C1
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RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
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RCC->APB1RSTR = 0;
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i2cObjectInit(&I2CD1);
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I2CD1.id_i2c = I2C1;
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#endif
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#if STM32_I2C_USE_I2C2
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RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2
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RCC->APB1RSTR = 0;
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i2cObjectInit(&I2CD2);
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I2CD2.id_i2c = I2C2;
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#endif
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}
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/**
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* @brief Configures and activates the I2C peripheral.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*/
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void i2c_lld_start(I2CDriver *i2cp) {
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/* If in stopped state then enables the I2C clock.*/
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if (i2cp->id_state == I2C_STOP) {
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#if STM32_I2C_USE_I2C1
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if (&I2CD1 == i2cp) {
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NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
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NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable
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}
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#endif
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#if STM32_I2C_USE_I2C2
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if (&I2CD2 == i2cp) {
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NVICEnableVector(I2C2_EV_IRQn, STM32_I2C2_IRQ_PRIORITY);
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NVICEnableVector(I2C2_ER_IRQn, STM32_I2C2_IRQ_PRIORITY);
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RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable
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}
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#endif
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}
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/* I2C setup.*/
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i2cp->id_i2c->CR1 = I2C_CR1_SWRST; // reset i2c peripherial
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i2cp->id_i2c->CR1 = 0;
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i2cp->id_i2c->CR1 = i2cp->id_config->i2cc_cr1;
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i2cp->id_i2c->CR2 = i2cp->id_config->i2cc_cr2 |
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I2C_CR2_ITERREN |
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I2C_CR2_ITEVTEN |
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I2C_CR2_ITBUFEN |
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36; //TODO: replace this by macro calculation
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/* TODO:
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* 1. macro timing calculator
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* 2. parameter checker
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* 3. definitions in halconf.h: i2c-freq, i2c_mode, etc
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* 4. trise time calculator/checker
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*/
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i2cp->id_i2c->CCR = i2cp->id_config->i2cc_ccr | 180;
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i2cp->id_i2c->TRISE = i2cp->id_config->i2cc_trise | 37;
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i2cp->id_i2c->CR1 |= 1; // enable interface
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}
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/**
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* @brief Deactivates the I2C peripheral.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*/
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void i2c_lld_stop(I2CDriver *i2cp) {
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/* If in ready state then disables the I2C clock.*/
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if (i2cp->id_state == I2C_READY) {
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#if STM32_I2C_USE_I2C1
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if (&I2CD1 == i2cp) {
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NVICDisableVector(I2C1_EV_IRQn);
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NVICDisableVector(I2C1_ER_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
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}
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#endif
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#if STM32_I2C_USE_I2C2
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if (&I2CD2 == i2cp) {
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NVICDisableVector(I2C2_EV_IRQn);
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NVICDisableVector(I2C2_ER_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
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}
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#endif
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}
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i2cp->id_state = I2C_STOP;
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}
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/* helper function, not API
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* write bytes in DR register
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* return TRUE if last byte written
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*/
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bool_t i2c_lld_txbyte(I2CDriver *i2cp) {
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if (i2cp->id_slave_config->txbufhead < i2cp->id_slave_config->txbytes){
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i2cp->id_i2c->DR = i2cp->id_slave_config->txbuf[i2cp->id_slave_config->txbufhead];
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(i2cp->id_slave_config->txbufhead)++;
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return(FALSE);
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}
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i2cp->id_slave_config->txbufhead = 0;
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return(TRUE); // last byte written
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}
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/* helper function, not API
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* read bytes from DR register
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* return TRUE if last byte read
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*/
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bool_t i2c_lld_rxbyte(I2CDriver *i2cp) {
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// temporal variables
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#define rxbuf i2cp->id_slave_config->rxbuf
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#define rxbufhead i2cp->id_slave_config->rxbufhead
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#define rxdepth i2cp->id_slave_config->rxdepth
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#define rxbytes i2cp->id_slave_config->rxbytes
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/* In order to generate the non-acknowledge pulse after the last received
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* data byte, the ACK bit must be cleared just after reading the second
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* last data byte (after second last RxNE event).
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*/
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if (rxbufhead < rxbytes){
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rxbuf[rxbufhead] = i2cp->id_i2c->DR;
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if ((rxbytes - rxbufhead) <= 2){
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i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);// clear ACK bit for automatically send NACK
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}
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rxbufhead++;
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return(FALSE);
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}
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rxbuf[rxbufhead] = i2cp->id_i2c->DR; // read last byte
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rxbufhead = 0;
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#undef rxbuf
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#undef rxbufhead
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#undef rxdepth
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#undef rxbytes
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return(TRUE); // last byte read
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}
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void i2c_lld_master_start(I2CDriver *i2cp){
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i2cp->id_i2c->CR1 |= I2C_CR1_START;
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}
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void i2c_lld_master_stop(I2CDriver *i2cp){
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i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
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chSysLock();
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while (i2cp->id_i2c->CR1 & I2C_CR1_STOP);
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chSysUnlock();
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}
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void i2c_lld_master_transmitI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
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i2cp->id_slave_config = i2cscfg;
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i2cp->id_slave_config->rw_bit = I2C_WRITE;
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// generate start condition. Later transmission goes in background
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i2c_lld_master_start(i2cp);
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}
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void i2c_lld_master_receiveI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
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i2cp->id_slave_config = i2cscfg;
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i2cp->id_slave_config->rw_bit = I2C_READ;
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// generate (re)start condition. Later connection goes asynchronously
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i2c_lld_master_start(i2cp);
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}
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/**
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* @brief Transmits data ever the I2C bus as masteri2cp.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
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* @param[in] restart bool. If TRUE then generate restart condition insted of stop
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*/
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void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart) {
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//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
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int i = 0;
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i2cp->id_slave_config = i2cscfg;
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i2cp->id_slave_config->rw_bit = I2C_WRITE;
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i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
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i++; // wait Address sent
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}
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i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_WRITE; // write slave addres in DR
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
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i++; // wait Address sent
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}
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i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
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i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
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// now write data byte by byte in DR register
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uint32_t n = 0;
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for (n = 0; n < i2cp->id_slave_config->txbytes; n++){
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i2cp->id_i2c->DR = i2cscfg->txbuf[n];
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
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i++;
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}
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}
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
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i++;
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}
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if (restart){
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i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
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i++; // wait start bit
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}
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}
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else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // generate stop condition
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}
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/**
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* @brief Receives data from the I2C bus.
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* @details Before receive data from I2C slave you must manually sent them some
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* control bytes first (refer to you device datasheet).
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
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*/
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void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
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chSysLock();
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i2cp->id_slave_config = i2cscfg;
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uint16_t i = 0;
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uint16_t tmp = 0;
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// send slave addres with read-bit
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i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_READ;
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
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i++; // wait Address sent
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}
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i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
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i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
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// set ACK bit
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i2cp->id_i2c->CR1 |= I2C_CR1_ACK;
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// collect data from slave
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for (i = 0; i < i2cp->id_slave_config->rxbytes; i++){
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if ((i2cp->id_slave_config->rxbytes - i) == 1){ // TODO: is it better <= in place of == ?
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// clear ACK bit for automatically send NACK
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i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);}
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while (!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
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tmp++;
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}
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i2cp->id_slave_config->rxbuf[i] = i2cp->id_i2c->DR;
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}
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// generate STOP
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i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
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chSysUnlock();
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}
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#endif // HAL_USE_I2C
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