140 lines
6.9 KiB
Plaintext
140 lines
6.9 KiB
Plaintext
/**
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* @defgroup ARM7 ARM7TDMI
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* @{
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* @details The ARM7 architecture is quite complex for a microcontroller and
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* some explanations are required about the port choices.
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*
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* @section ARM7_NOTES The ARM7 modes
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* The ARM7 port supports three modes:
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* - Pure ARM mode, this is the preferred mode for code speed. The code size
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* is larger however. This mode is enabled when all the modules are compiled
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* in ARM mode, see the Makefiles.
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* - Pure THUMB mode, this is the preferred mode for code size. In this mode
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* the execution speed is slower than the ARM mode. This mode is enabled
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* when all the modules are compiled in THUMB mode, see the Makefiles.
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* - Interworking mode, when in the system there are ARM modules mixed with
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* THUMB modules then the interworking compiler option is enabled. This is
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* usually the slowest mode and the code size is not as good as in pure
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* THUMB mode.
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*
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* @section ARM7_STATES Mapping of the System States in the ARM7 port
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM7
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* port:
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* - <b>Initialization</b>. This state is represented by the startup code and
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* the initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated, usually the CPU goes through several
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* hardware states during the startup phase.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state the ARM7TDMI has both the interrupt sources
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* (IRQ and FIQ) enabled and is running in ARM System Mode.
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* - <b>Suspended</b>. In this state the IRQ sources are disabled but the FIQ
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* sources are served, the core is running in ARM System Mode.
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* - <b>Disabled</b>. Both the IRQ and FIQ sources are disabled, the core is
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* running in ARM System Mode.
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* - <b>Sleep</b>. The ARM7 code does not have any built-in low power mode but
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* there are clock stop modes implemented in custom ways by the various
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* silicon vendors. This state is implemented in each microcontroller support
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* code in a different way, the core is running (or freezed...) in ARM
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* System Mode.
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* - <b>S-Locked</b>. IRQ sources disabled, core running in ARM System Mode.
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* - <b>I-Locked</b>. IRQ sources disabled, core running in ARM IRQ Mode. Note
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* that this state is not different from the SRI state in this port, the
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* @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
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* order to formally change state because this may change).
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* - <b>Serving Regular Interrupt</b>. IRQ sources disabled, core running in
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* ARM IRQ Mode. See also the I-Locked state.
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* - <b>Serving Fast Interrupt</b>. IRQ and FIQ sources disabled, core running
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* in ARM FIQ Mode.
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* - <b>Serving Non-Maskable Interrupt</b>. There are no asynchronous NMI
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* sources in ARM7 architecture but synchronous SVC, ABT and UND exception
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* handlers can be seen as belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after disabling both IRQ
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* and FIQ sources. The ARM state is whatever the processor was running when
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* @p chSysHalt() was invoked.
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*
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* @section ARM7_NOTES The ARM7 port notes
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* The ARM7 port makes some assumptions on the application code organization:
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* - The @p main() function is invoked in system mode.
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* - Each thread has a private user/system stack, the system has a single
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* interrupt stack where all the interrupts are processed.
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* - The threads are started in system mode.
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* - The threads code can run in system mode or user mode, however the
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* code running in user mode cannot invoke the ChibiOS/RT APIs directly
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* because privileged instructions are used inside.<br>
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* The kernel APIs can be eventually invoked by using a SWI entry point
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* that handles the switch in system mode and the return in user mode.
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* - Other modes are not preempt-able because the system code assumes the
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* threads running in system mode. When running in supervisor or other
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* modes make sure that the interrupts are globally disabled.
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* - Interrupts nesting is not supported in the ARM7 code because their
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* implementation, even if possible, is not really efficient in this
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* architecture.
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* - FIQ sources can preempt the kernel (by design) so it is not possible to
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* invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not
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* affected by the kernel activity so there is not added jitter.
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*
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* @section ARM7_IH ARM7 Interrupt Handlers
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* ARM7 Interrupt handlers do not save function-saved registers so you need to
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* make sure your code saves them or does not use them (this happens
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* because in the ARM7 port all the OS interrupt handler functions are declared
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* naked).<br>
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* Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the
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* system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().<br>
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* The easiest way to ensure this is to just invoke a normal function from
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* within the interrupt handler, the function code will save all the required
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* registers.<br>
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* Example:
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* @code
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* CH_IRQ_HANDLER void irq_handler(void) {
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* CH_IRQ_PROLOGUE();
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*
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* serve_interrupt();
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*
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* VICVectAddr = 0; // This is LPC214x-specific.
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* CH_IRQ_EPILOGUE();
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* }
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* @endcode
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* This is not a bug but an implementation choice, this solution allows to
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* have interrupt handlers compiled in thumb mode without have to use an
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* interworking mode (the mode switch is hidden in the macros), this
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* greatly improves code efficiency and size. You can look at the serial
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* driver for real examples of interrupt handlers.
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*
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* @ingroup Ports
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*/
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/** @} */
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/**
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* @defgroup ARM7CONF Configuration Options
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* @{
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* @brief ARM7 specific configuration options.
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* @details The ARM7 port allows some architecture-specific configurations
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* settings that can be specified externally, as example on the compiler
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* command line:
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* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
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* by an interrupt handler between the @p extctx and @p intctx
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* structures.<br>
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* In practice this value is the stack space used by the chSchDoReschedule()
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* stack frame.<br>
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* This value can be affected by a variety of external things like compiler
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* version, compiler options, kernel settings (speed/size) and so on.<br>
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* The default for this value is @p 0x10 which should be a safe value, you
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* can trim this down by defining the macro externally. This would save
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* some valuable RAM space for each thread present in the system.<br>
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* The default value is set into <b>./ports/ARM7/chcore.h</b>.
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*
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* @ingroup ARM7
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*/
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/** @} */
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/**
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* @defgroup ARM7_CORE ARM7 Core Implementation
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* @{
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* @brief ARM7 specific port code, structures and macros.
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*
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* @ingroup ARM7
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* @file ports/ARM7/chcore.h Port related structures and macros.
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* @file ports/ARM7/chtypes.h Port types.
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*/
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/** @} */
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