189 lines
5.2 KiB
C
189 lines
5.2 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for Raisonance REva V3 + STM8S208RB daughter board.
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*/
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/*
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* Board identifiers.
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*/
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#define BOARD_REVA_V3_STM8S208RB
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#define BOARD_NAME "Raisonance REva V3 + STM8S208RB"
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/*
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* Board frequencies.
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*/
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#define HSECLK 0
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/*
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* MCU model used on the board.
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*/
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#define STM8S208
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/*
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* Pin definitions.
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*/
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#define PA_OSCIN 1
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#define PA_J2_25 2 /* It is also OSCOUT. */
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#define PA_J2_27 3
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#define PA_RX 4
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#define PA_TX 5
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#define PB_LED(n) (n)
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#define PB_LCD_D0 0
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#define PB_LCD_D1 1
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#define PB_LCD_CSB 2
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#define PB_LCD_RESB 3
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#define PC_ADC_ETR 0
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#define PC_J2_51 1
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#define PC_J2_53 2
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#define PC_J2_55 3
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#define PC_J2_57 4
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#define PC_SCK 5
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#define PC_MOSI 6
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#define PC_MISO 7
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#define PD_J2_69 0
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#define PD_J2_21 1
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#define PD_J2_67 2
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#define PD_J2_65 3
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#define PD_PWM 4
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#define PD_J2_63 5
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#define PD_J2_61 6
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#define PD_J2_59 7
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#define PE_P2_49 0
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#define PE_SCL 1
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#define PE_SDA 2
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#define PE_P2_47 3
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#define PE_P2_45 4
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#define PE_P2_43 5
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#define PE_P2_41 6
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#define PE_P2_39 7
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#define PF_J2_37 0
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#define PF_J2_35 1
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#define PF_J2_33 2
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#define PF_J2_31 3
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#define PF_ANA_IN1 4
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#define PF_ANA_IN2 5
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#define PF_ANA_TEMP 6
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#define PF_ANA_POT 7
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#define PG_CAN_TX 0
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#define PG_CAN_RX 1
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#define PG_BT5 2
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#define PG_BT6 3
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#define PG_SW4 4
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#define PG_SW3 5
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#define PG_SW2 6
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#define PG_SW1 7
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#define PI_J2_71 0
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/*
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* Port A initial setup.
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*/
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#define VAL_GPIOAODR (1 << PA_TX) /* PA_TX initially to 1. */
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#define VAL_GPIOADDR (1 << PA_TX) /* PA_TX output, others inputs. */
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#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */
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#define VAL_GPIOACR2 0
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/*
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* Port B initial setup.
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*/
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#define VAL_GPIOBODR 0xFF /* Initially all set to high. */
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#define VAL_GPIOBDDR 0xFF /* All outputs. */
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#define VAL_GPIOBCR1 0xFF /* All push-pull. */
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#define VAL_GPIOBCR2 0
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/*
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* Port C initial setup.
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*/
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#define VAL_GPIOCODR 0
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#define VAL_GPIOCDDR 0 /* All inputs. */
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#define VAL_GPIOCCR1 0xFF /* All pull-up. */
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#define VAL_GPIOCCR2 0
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/*
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* Port D initial setup.
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*/
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#define VAL_GPIODODR 0
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#define VAL_GPIODDDR 0 /* All inputs. */
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#define VAL_GPIODCR1 0xFF /* All pull-up. */
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#define VAL_GPIODCR2 0
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/*
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* Port E initial setup.
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*/
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#define VAL_GPIOEODR 0
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#define VAL_GPIOEDDR 0 /* All inputs. */
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#define VAL_GPIOECR1 0xFF /* All pull-up. */
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#define VAL_GPIOECR2 0
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/*
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* Port F initial setup.
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*/
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#define VAL_GPIOFODR 0
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#define VAL_GPIOFDDR 0 /* All inputs. */
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#define VAL_GPIOFCR1 0xFF /* All pull-up. */
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#define VAL_GPIOFCR2 0
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/*
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* Port G initial setup.
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*/
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#define VAL_GPIOGODR (1 << PG_CAN_TX)/* CAN_TX initially to 1. */
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#define VAL_GPIOGDDR (1 << PG_CAN_TX)/* CAN_TX output, others inputs. */
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#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */
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#define VAL_GPIOGCR2 0
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/*
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* Port H initial setup (dummy, not present).
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*/
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#define VAL_GPIOHODR 0
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#define VAL_GPIOHDDR 0 /* All inputs. */
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#define VAL_GPIOHCR1 0xFF /* All pull-up. */
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#define VAL_GPIOHCR2 0
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/*
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* Port I initial setup.
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*/
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#define VAL_GPIOIODR 0
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#define VAL_GPIOIDDR 0 /* All inputs. */
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#define VAL_GPIOICR1 0xFF /* All pull-up. */
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#define VAL_GPIOICR2 0
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FROM_ASM_ */
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#endif /* _BOARD_H_ */
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