Перепланировка на двусторонний монтаж

4 layers

Update hellen1-vr-discrete.kicad_pcb

Обновила контур, доработка внутри

класс цепей

сквозные пады GND
This commit is contained in:
Nadezhda-n 2022-10-18 22:30:55 +03:00
parent 7ef8c3fdd5
commit 687a129a55
3 changed files with 8860 additions and 6828 deletions

File diff suppressed because it is too large Load Diff

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@ -1,7 +1,7 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "Все слои",
"active_layer": 31,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
@ -10,7 +10,7 @@
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
"zones": 0.4000000059604645
},
"ratsnest_display_mode": 0,
"selection_filter": {
@ -24,7 +24,7 @@
"text": true,
"tracks": true,
"vias": true,
"zones": true
"zones": false
},
"visible_items": [
0,
@ -33,7 +33,6 @@
3,
4,
5,
6,
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10,
@ -63,7 +62,7 @@
35,
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"visible_layers": "fffffff_ffffffff",
"visible_layers": "ffcfdfc_ffffffff",
"zone_display_mode": 0
},
"meta": {

View File

@ -33,9 +33,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.3,
"drill": 0.0,
"height": 0.6,
"width": 0.6
"width": 1.2
},
"silk_line_width": 0.12,
"silk_text_italic": false,
@ -70,6 +70,7 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
@ -88,6 +89,7 @@
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
@ -114,7 +116,8 @@
"min_through_hole_diameter": 0.3,
"min_track_width": 0.1651,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
@ -320,6 +323,7 @@
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
@ -359,7 +363,7 @@
"classes": [
{
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"clearance": 0.1651,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -373,10 +377,31 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.4,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "WR",
"nets": [
"VR+",
"VR-"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
}
],
"meta": {
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"version": 2
},
"net_colors": null
},
@ -392,6 +417,7 @@
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
@ -405,20 +431,24 @@
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
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},
"net_format_name": "",
"ngspice": {
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"meta": {
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},
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"page_layout_descr_file": "",
"plot_directory": "gerber",