Перепланировка на двусторонний монтаж
4 layers Update hellen1-vr-discrete.kicad_pcb Обновила контур, доработка внутри класс цепей сквозные пады GND
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@ -1,7 +1,7 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "Все слои",
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"active_layer": 31,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_nets": [],
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"high_contrast_mode": 0,
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@ -10,7 +10,7 @@
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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"zones": 0.4000000059604645
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},
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"ratsnest_display_mode": 0,
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"selection_filter": {
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@ -24,7 +24,7 @@
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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"zones": false
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},
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"visible_items": [
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0,
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@ -33,7 +33,6 @@
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3,
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4,
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5,
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6,
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8,
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9,
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10,
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@ -63,7 +62,7 @@
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35,
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36
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],
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"visible_layers": "fffffff_ffffffff",
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"visible_layers": "ffcfdfc_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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@ -33,9 +33,9 @@
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.3,
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"drill": 0.0,
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"height": 0.6,
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"width": 0.6
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"width": 1.2
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},
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"silk_line_width": 0.12,
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"silk_text_italic": false,
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@ -70,6 +70,7 @@
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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@ -88,6 +89,7 @@
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"silk_over_copper": "error",
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"silk_overlap": "error",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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@ -114,7 +116,8 @@
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.1651,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997
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"min_via_diameter": 0.39999999999999997,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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@ -320,6 +323,7 @@
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],
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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@ -359,7 +363,7 @@
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.1651,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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@ -373,10 +377,31 @@
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.4,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "WR",
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"nets": [
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"VR+",
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"VR-"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6.0
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}
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],
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"meta": {
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"version": 0
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"version": 2
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},
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"net_colors": null
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},
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@ -392,6 +417,7 @@
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"page_layout_descr_file": ""
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},
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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@ -405,20 +431,24 @@
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"intersheets_ref_show": false,
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"intersheets_ref_suffix": "",
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"junction_size_choice": 3,
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"label_size_ratio": 0.3,
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"pin_symbol_size": 25.0,
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"text_offset_ratio": 0.3
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},
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"legacy_lib_dir": "",
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"legacy_lib_list": [],
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"meta": {
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"version": 0
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"version": 1
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},
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"net_format_name": "",
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"ngspice": {
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"fix_include_paths": true,
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"fix_passive_vals": false,
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"meta": {
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"version": 0
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},
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"model_mode": 0
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"model_mode": 0,
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"workbook_filename": ""
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},
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"page_layout_descr_file": "",
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"plot_directory": "gerber",
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