55 lines
1.1 KiB
Prolog
55 lines
1.1 KiB
Prolog
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update=Пт 13 июн 2014 14:13:29
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version=1
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last_client=cvpcb
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[general]
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version=1
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[eeschema]
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version=1
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LibDir=../rusefi_lib
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NetFmtName=PcbnewAdvanced
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RptD_X=0
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RptD_Y=100
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RptLab=1
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LabSize=60
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=conn
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LibName4=logo_flipped
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LibName5=art-electro-ic
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[pcbnew]
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version=1
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LastNetListRead=adc_amp_divider.net
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UseCmpFile=0
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PadDrill=" 1,016000"
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PadDrillOvalY=" 1,016000"
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PadSizeH=" 1,524000"
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PadSizeV=" 1,524000"
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PcbTextSizeV=" 1,500000"
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PcbTextSizeH=" 1,500000"
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PcbTextThickness=" 0,300000"
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ModuleTextSizeV=" 1,000000"
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ModuleTextSizeH=" 1,000000"
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ModuleTextSizeThickness=" 0,150000"
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SolderMaskClearance=" 0,000000"
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SolderMaskMinWidth=" 0,000000"
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DrawSegmentWidth=" 0,100000"
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BoardOutlineThickness=" 0,100000"
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ModuleOutlineThickness=" 0,150000"
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[pcbnew/libraries]
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LibName1=connect
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LibName2=discret
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LibName3=pin_array
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LibName4=smd_capacitors
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LibName5=smd_transistors
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LibName6=libcms
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LibName7=art-electro-conn
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LibName8=logo_flipped
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LibName9=led
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LibDir=../rusefi_lib
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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