54 lines
1.1 KiB
Prolog
54 lines
1.1 KiB
Prolog
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update=2/29/2016 8:07:21 PM
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last_client=kicad
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[common]
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NetDir=
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[general]
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version=1
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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[schematic_editor]
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version=1
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PageLayoutDescrFile=C:/Users/Vista_64_D630/Desktop/Jared/code/Hardware/trunk/rusefi.com/rusefi_lib/Border.kicad_wks
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceForceRefPrefix=0
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SpiceUseNetNumbers=0
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LabSize=60
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[eeschema]
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version=1
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LibDir=../rusefi_lib
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[eeschema/libraries]
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LibName1=KICAD_Older_Version
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LibName2=power
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LibName3=device
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LibName4=conn
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LibName5=linear
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LibName6=interface
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LibName7=logo_flipped
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LibName8=max9939
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LibName9=MAX9926-9927
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[pcbnew]
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version=1
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PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
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LastNetListRead=vrs_io_1.net
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PadDrill=0.6
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PadDrillOvalY=0.6
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PadSizeH=0.35052
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PadSizeV=0.70104
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PcbTextSizeV=2.032
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PcbTextSizeH=1.524
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PcbTextThickness=0.4318
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ModuleTextSizeV=1.524
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ModuleTextSizeH=1.524
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ModuleTextSizeThickness=0.254
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SolderMaskClearance=0.254
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SolderMaskMinWidth=0
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DrawSegmentWidth=0.254
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BoardOutlineThickness=0.254
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ModuleOutlineThickness=0.09906
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