Prepare for MFS on internal flash (#5686)

* Rename EFI_STORAGE_EXT_SNOR to EFI_STORAGE_MFS

Just to reduce confusion. MFS is going to be used for AT32 internal
flash.

* MFS: hide low level stuff to board file

MFS can be located on internal or external flash/eeprom.
This is board-dependent, so hide intialization and configuration
to board file.
This should also help switching to MFS on internal flash too.

* Fix simulator

* Fix comments
This commit is contained in:
Andrey G 2023-11-03 14:30:31 +03:00 committed by GitHub
parent 19de6c1bcc
commit 1eea6c946b
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 80 additions and 51 deletions

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@ -1,5 +1,6 @@
# List of all the board related files.
BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp
BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp \
$(BOARD_DIR)/board_storage.cpp
# Required include directories
BOARDINC += $(BOARD_DIR)/config/controllers/algo

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@ -0,0 +1,58 @@
/**
* @file boards/subaru_eg33/board_storage.h
*
* @brief Storage configuration file
*
* @date Nov 03, 2023
* @author Andrey Gusakov, 2023
*/
#include "pch.h"
/* This board stores settings in external QSPI flash */
#if EFI_STORAGE_MFS == TRUE
#include "hal_serial_nor.h"
#include "hal_mfs.h"
/* Some fields in following struct are used for DMA transfers, so do not cache */
NO_CACHE SNORDriver snor1;
const WSPIConfig WSPIcfg1 = {
.end_cb = NULL,
.error_cb = NULL,
.dcr = STM32_DCR_FSIZE(23U) | /* 8MB device. */
STM32_DCR_CSHT(1U) /* NCS 2 cycles delay. */
};
const SNORConfig snorcfg1 = {
.busp = &WSPID1,
.buscfg = &WSPIcfg1
};
const MFSConfig mfsd_nor_config = {
.flashp = (BaseFlash *)&snor1,
.erased = 0xFFFFFFFFU,
.bank_size = 64 * 1024U,
.bank0_start = 0U,
.bank0_sectors = 128U, /* 128 * 4 K = 0.5 Mb */
.bank1_start = 128U,
.bank1_sectors = 128U
};
void boardInitMfs()
{
#if SNOR_SHARED_BUS == FALSE
wspiStart(&WSPID1, &WSPIcfg1);
#endif
/* Initializing and starting snor1 driver.*/
snorObjectInit(&snor1);
snorStart(&snor1, &snorcfg1);
}
const MFSConfig *boardGetMfsConfig()
{
return &mfsd_nor_config;
}
#endif /* EFI_STORAGE_MFS == TRUE */

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@ -103,8 +103,8 @@
#define EFI_NARROW_EGO_AVERAGING TRUE
/* this board has external QSPI NOR flash */
#undef EFI_STORAGE_EXT_SNOR
#define EFI_STORAGE_EXT_SNOR TRUE
#undef EFI_STORAGE_MFS
#define EFI_STORAGE_MFS TRUE
#undef EFI_STORAGE_INT_FLASH
#define EFI_STORAGE_INT_FLASH FALSE

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@ -453,8 +453,8 @@
#define EFI_STORAGE_INT_FLASH TRUE
#endif
#ifndef EFI_STORAGE_EXT_SNOR
#define EFI_STORAGE_EXT_SNOR FALSE
#ifndef EFI_STORAGE_MFS
#define EFI_STORAGE_MFS FALSE
#endif
#ifndef EFI_SENT_SUPPORT

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@ -21,8 +21,7 @@
#include "tunerstudio.h"
#endif
#if EFI_STORAGE_EXT_SNOR == TRUE
#include "hal_serial_nor.h"
#if EFI_STORAGE_MFS == TRUE
#include "hal_mfs.h"
#endif
@ -30,39 +29,17 @@
static bool needToWriteConfiguration = false;
/* if we store settings externally */
#if EFI_STORAGE_EXT_SNOR == TRUE
/* if we use ChibiOS MFS for settings */
#if EFI_STORAGE_MFS == TRUE
/* Some fields in following struct is used for DMA transfers, so do no cache */
NO_CACHE SNORDriver snor1;
const WSPIConfig WSPIcfg1 = {
.end_cb = NULL,
.error_cb = NULL,
.dcr = STM32_DCR_FSIZE(23U) | /* 8MB device. */
STM32_DCR_CSHT(1U) /* NCS 2 cycles delay. */
};
const SNORConfig snorcfg1 = {
.busp = &WSPID1,
.buscfg = &WSPIcfg1
};
/* Managed Flash Storage stuff */
/* Managed Flash Storage driver */
MFSDriver mfsd;
const MFSConfig mfsd_nor_config = {
.flashp = (BaseFlash *)&snor1,
.erased = 0xFFFFFFFFU,
.bank_size = 64 * 1024U,
.bank0_start = 0U,
.bank0_sectors = 128U, /* 128 * 4 K = 0.5 Mb */
.bank1_start = 128U,
.bank1_sectors = 128U
};
#define EFI_MFS_SETTINGS_RECORD_ID 1
extern void boardInitMfs(void);
extern const MFSConfig *boardGetMfsConfig(void);
#endif
/**
@ -79,7 +56,7 @@ static uint32_t flashStateCrc(const persistent_config_container_s& state) {
#if EFI_FLASH_WRITE_THREAD
chibios_rt::BinarySemaphore flashWriteSemaphore(/*taken =*/ true);
#if EFI_STORAGE_EXT_SNOR == TRUE
#if EFI_STORAGE_MFS == TRUE
/* in case of MFS we need more stack */
static THD_WORKING_AREA(flashWriteStack, 3 * UTILITY_THREAD_STACK_SIZE);
#else
@ -103,7 +80,7 @@ void setNeedToWriteConfiguration() {
needToWriteConfiguration = true;
#if EFI_FLASH_WRITE_THREAD
if (allowFlashWhileRunning() || (EFI_STORAGE_EXT_SNOR == TRUE)) {
if (allowFlashWhileRunning() || (EFI_STORAGE_MFS == TRUE)) {
// Signal the flash writer thread to wake up and write at its leisure
flashWriteSemaphore.signal();
}
@ -169,7 +146,7 @@ void writeToFlashNow() {
persistentState.version = FLASH_DATA_VERSION;
persistentState.crc = flashStateCrc(persistentState);
#if EFI_STORAGE_EXT_SNOR == TRUE
#if EFI_STORAGE_MFS == TRUE
mfs_error_t err;
/* In case of MFS:
* do we need to have two copies?
@ -259,7 +236,7 @@ static FlashState readOneConfigurationCopy(flashaddr_t address) {
* in this method we read first copy of configuration in flash. if that first copy has CRC or other issues we read second copy.
*/
static FlashState readConfiguration() {
#if EFI_STORAGE_EXT_SNOR == TRUE
#if EFI_STORAGE_MFS == TRUE
size_t settings_size = sizeof(persistentState);
mfs_error_t err = mfsReadRecord(&mfsd, EFI_MFS_SETTINGS_RECORD_ID,
&settings_size, (uint8_t *)&persistentState);
@ -347,20 +324,13 @@ static void rewriteConfig() {
}
void initFlash() {
#if EFI_STORAGE_EXT_SNOR == TRUE
mfs_error_t err;
#if SNOR_SHARED_BUS == FALSE
wspiStart(&WSPID1, &WSPIcfg1);
#endif
/* Initializing and starting snor1 driver.*/
snorObjectInit(&snor1);
snorStart(&snor1, &snorcfg1);
#if EFI_STORAGE_MFS == TRUE
boardInitMfs();
const MFSConfig *config = boardGetMfsConfig();
/* MFS */
mfsObjectInit(&mfsd);
err = mfsStart(&mfsd, &mfsd_nor_config);
mfs_error_t err = mfsStart(&mfsd, config);
if (err < MFS_NO_ERROR) {
/* hm...? */
}

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@ -146,7 +146,7 @@
#define EFI_INTERNAL_FLASH TRUE
#define EFI_STORAGE_INT_FLASH TRUE
#define EFI_FLASH_WRITE_THREAD TRUE
#define EFI_STORAGE_EXT_SNOR FALSE
#define EFI_STORAGE_MFS FALSE
#define EFI_RTC FALSE
#define EFI_MALFUNCTION_INDICATOR FALSE
#define EFI_LOGIC_ANALYZER FALSE