consolidate stm32 mpu util (#2314)
Co-authored-by: Matthew Kennedy <makenne@microsoft.com>
This commit is contained in:
Matthew Kennedy
GitHub
parent
3debd2229b
commit
36483e870a
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@ -6,7 +6,7 @@
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* @author Andrey Belomutskiy, (c) 2012-2020
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*/
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#include "global.h"
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#include "engine_ptr.h"
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#include "efi_gpio.h"
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#include "expected.h"
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@ -29,6 +29,8 @@
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#include "backup_ram.h"
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#endif /* EFI_PROD_CODE */
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EXTERN_ENGINE;
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#if HAL_USE_ADC
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// ADC_CHANNEL_IN0 // PA0
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@ -383,4 +385,348 @@ void baseMCUInit(void) {
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BOR_Set(BOR_Level_1); // one step above default value
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}
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extern "C" {
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void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress);
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}
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extern uint32_t __main_stack_base__;
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#define GET_CFSR() (*((volatile uint32_t *) (0xE000ED28)))
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typedef struct port_intctx intctx_t;
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EXTERNC int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK
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// this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655
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// coverity[uninit_use]
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register intctx_t *r13 asm ("r13");
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otp->activeStack = r13;
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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// ISR context
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remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__;
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} else {
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remainingStack = (int)(r13 - 1) - (int)otp->wabase;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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UNUSED(otp);
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return 99999;
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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}
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void _unhandled_exception(void) {
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/*lint -restore*/
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chDbgPanic3("_unhandled_exception", __FILE__, __LINE__);
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while (true) {
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}
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}
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void DebugMonitorVector(void) {
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chDbgPanic3("DebugMonitorVector", __FILE__, __LINE__);
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while (TRUE)
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;
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}
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void UsageFaultVector(void) {
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chDbgPanic3("UsageFaultVector", __FILE__, __LINE__);
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while (TRUE)
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;
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}
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void BusFaultVector(void) {
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chDbgPanic3("BusFaultVector", __FILE__, __LINE__);
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while (TRUE) {
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}
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}
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/**
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+ * @brief Register values for postmortem debugging.
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+ */
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volatile uint32_t postmortem_r0;
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volatile uint32_t postmortem_r1;
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volatile uint32_t postmortem_r2;
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volatile uint32_t postmortem_r3;
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volatile uint32_t postmortem_r12;
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volatile uint32_t postmortem_lr; /* Link register. */
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volatile uint32_t postmortem_pc; /* Program counter. */
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volatile uint32_t postmortem_psr;/* Program status register. */
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volatile uint32_t postmortem_CFSR;
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volatile uint32_t postmortem_HFSR;
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volatile uint32_t postmortem_DFSR;
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volatile uint32_t postmortem_AFSR;
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volatile uint32_t postmortem_BFAR;
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volatile uint32_t postmortem_MMAR;
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volatile uint32_t postmortem_SCB_SHCSR;
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/**
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* @brief Evaluates to TRUE if system runs under debugger control.
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* @note This bit resets only by power reset.
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*/
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#define is_under_debugger() (((CoreDebug)->DHCSR) & \
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CoreDebug_DHCSR_C_DEBUGEN_Msk)
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/**
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*
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*/
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void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress) {
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postmortem_r0 = pulFaultStackAddress[0];
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postmortem_r1 = pulFaultStackAddress[1];
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postmortem_r2 = pulFaultStackAddress[2];
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postmortem_r3 = pulFaultStackAddress[3];
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postmortem_r12 = pulFaultStackAddress[4];
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postmortem_lr = pulFaultStackAddress[5];
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postmortem_pc = pulFaultStackAddress[6];
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postmortem_psr = pulFaultStackAddress[7];
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/* Configurable Fault Status Register. Consists of MMSR, BFSR and UFSR */
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postmortem_CFSR = GET_CFSR();
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/* Hard Fault Status Register */
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postmortem_HFSR = (*((volatile uint32_t *) (0xE000ED2C)));
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/* Debug Fault Status Register */
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postmortem_DFSR = (*((volatile uint32_t *) (0xE000ED30)));
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/* Auxiliary Fault Status Register */
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postmortem_AFSR = (*((volatile uint32_t *) (0xE000ED3C)));
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/* Read the Fault Address Registers. These may not contain valid values.
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Check BFARVALID/MMARVALID to see if they are valid values
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MemManage Fault Address Register */
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postmortem_MMAR = (*((volatile uint32_t *) (0xE000ED34)));
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/* Bus Fault Address Register */
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postmortem_BFAR = (*((volatile uint32_t *) (0xE000ED38)));
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postmortem_SCB_SHCSR = SCB->SHCSR;
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if (is_under_debugger()) {
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__asm("BKPT #0\n");
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// Break into the debugger
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}
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/* harmless infinite loop */
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while (1) {
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;
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}
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}
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void HardFaultVector(void) {
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#if 0 && defined __GNUC__
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" ldr r1, [r0, #24] \n"
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" ldr r2, handler2_address_const \n"
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" bx r2 \n"
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" handler2_address_const: .word prvGetRegistersFromStack \n"
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);
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#else
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#endif /* 0 && defined __GNUC__ */
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int cfsr = GET_CFSR();
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if (cfsr & 0x1) {
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chDbgPanic3("H IACCVIOL", __FILE__, __LINE__);
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} else if (cfsr & 0x100) {
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chDbgPanic3("H IBUSERR", __FILE__, __LINE__);
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} else if (cfsr & 0x20000) {
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chDbgPanic3("H INVSTATE", __FILE__, __LINE__);
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} else {
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chDbgPanic3("HardFaultVector", __FILE__, __LINE__);
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}
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while (TRUE) {
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}
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}
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#if HAL_USE_SPI
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bool isSpiInitialized[5] = { false, false, false, false, false };
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static int getSpiAf(SPIDriver *driver) {
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#if STM32_SPI_USE_SPI1
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if (driver == &SPID1) {
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return EFI_SPI1_AF;
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}
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#endif
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#if STM32_SPI_USE_SPI2
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if (driver == &SPID2) {
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return EFI_SPI2_AF;
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}
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#endif
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#if STM32_SPI_USE_SPI3
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if (driver == &SPID3) {
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return EFI_SPI3_AF;
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}
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#endif
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return -1;
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}
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brain_pin_e getMisoPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return CONFIG(spi1misoPin);
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case SPI_DEVICE_2:
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return CONFIG(spi2misoPin);
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case SPI_DEVICE_3:
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return CONFIG(spi3misoPin);
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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brain_pin_e getMosiPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return CONFIG(spi1mosiPin);
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case SPI_DEVICE_2:
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return CONFIG(spi2mosiPin);
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case SPI_DEVICE_3:
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return CONFIG(spi3mosiPin);
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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brain_pin_e getSckPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return CONFIG(spi1sckPin);
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case SPI_DEVICE_2:
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return CONFIG(spi2sckPin);
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case SPI_DEVICE_3:
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return CONFIG(spi3sckPin);
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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void turnOnSpi(spi_device_e device) {
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if (isSpiInitialized[device])
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return; // already initialized
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isSpiInitialized[device] = true;
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if (device == SPI_DEVICE_1) {
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// todo: introduce a nice structure with all fields for same SPI
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#if STM32_SPI_USE_SPI1
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// scheduleMsg(&logging, "Turning on SPI1 pins");
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initSpiModule(&SPID1, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi1SckMode,
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engineConfiguration->spi1MosiMode,
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engineConfiguration->spi1MisoMode);
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#endif /* STM32_SPI_USE_SPI1 */
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}
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if (device == SPI_DEVICE_2) {
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#if STM32_SPI_USE_SPI2
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// scheduleMsg(&logging, "Turning on SPI2 pins");
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initSpiModule(&SPID2, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi2SckMode,
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engineConfiguration->spi2MosiMode,
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engineConfiguration->spi2MisoMode);
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#endif /* STM32_SPI_USE_SPI2 */
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}
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if (device == SPI_DEVICE_3) {
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#if STM32_SPI_USE_SPI3
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// scheduleMsg(&logging, "Turning on SPI3 pins");
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initSpiModule(&SPID3, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi3SckMode,
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engineConfiguration->spi3MosiMode,
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engineConfiguration->spi3MisoMode);
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#endif /* STM32_SPI_USE_SPI3 */
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}
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if (device == SPI_DEVICE_4) {
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#if STM32_SPI_USE_SPI4
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// scheduleMsg(&logging, "Turning on SPI4 pins");
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/* there is no cofiguration fields for SPI4 in engineConfiguration, rely on board init code
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* it should set proper functions for SPI4 pins */
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#endif /* STM32_SPI_USE_SPI4 */
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}
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}
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void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso,
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brain_pin_e mosi,
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int sckMode,
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int mosiMode,
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int misoMode) {
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/**
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* See https://github.com/rusefi/rusefi/pull/664/
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*
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* Info on the silicon defect can be found in this document, section 2.5.2:
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* https://www.st.com/content/ccc/resource/technical/document/errata_sheet/0a/98/58/84/86/b6/47/a2/DM00037591.pdf/files/DM00037591.pdf/jcr:content/translations/en.DM00037591.pdf
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*/
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efiSetPadMode("SPI clock", sck, PAL_MODE_ALTERNATE(getSpiAf(driver)) | sckMode | PAL_STM32_OSPEED_HIGHEST);
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efiSetPadMode("SPI master out", mosi, PAL_MODE_ALTERNATE(getSpiAf(driver)) | mosiMode | PAL_STM32_OSPEED_HIGHEST);
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efiSetPadMode("SPI master in ", miso, PAL_MODE_ALTERNATE(getSpiAf(driver)) | misoMode | PAL_STM32_OSPEED_HIGHEST);
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}
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void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
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spiConfig->end_cb = nullptr;
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ioportid_t port = getHwPort("spi", csPin);
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ioportmask_t pin = getHwPin("spi", csPin);
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spiConfig->ssport = port;
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spiConfig->sspad = pin;
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efiSetPadMode("chip select", csPin, PAL_STM32_MODE_OUTPUT);
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}
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#endif /* HAL_USE_SPI */
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#if EFI_CAN_SUPPORT
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static bool isValidCan1RxPin(brain_pin_e pin) {
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return pin == GPIOA_11 || pin == GPIOB_8 || pin == GPIOD_0;
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}
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static bool isValidCan1TxPin(brain_pin_e pin) {
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return pin == GPIOA_12 || pin == GPIOB_9 || pin == GPIOD_1;
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}
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static bool isValidCan2RxPin(brain_pin_e pin) {
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return pin == GPIOB_5 || pin == GPIOB_12;
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}
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static bool isValidCan2TxPin(brain_pin_e pin) {
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return pin == GPIOB_6 || pin == GPIOB_13;
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}
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bool isValidCanTxPin(brain_pin_e pin) {
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return isValidCan1TxPin(pin) || isValidCan2TxPin(pin);
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}
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bool isValidCanRxPin(brain_pin_e pin) {
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return isValidCan1RxPin(pin) || isValidCan2RxPin(pin);
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}
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CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) {
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#if STM32_CAN_USE_CAN1
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if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx))
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return &CAND1;
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#endif
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#if STM32_CAN_USE_CAN2
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if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx))
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return &CAND2;
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#endif
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return NULL;
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}
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#endif /* EFI_CAN_SUPPORT */
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#endif // EFI_PROD_CODE
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@ -5,386 +5,7 @@
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* @author Andrey Belomutskiy, (c) 2012-2020
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*/
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#include "global.h"
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#if EFI_PROD_CODE
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#include "mpu_util.h"
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#include "flash_int.h"
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#include "engine.h"
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#include "pin_repository.h"
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#include "stm32f4xx_hal_flash.h"
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#include "os_util.h"
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EXTERN_ENGINE;
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extern "C" {
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void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress);
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}
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extern uint32_t __main_stack_base__;
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#define GET_CFSR() (*((volatile uint32_t *) (0xE000ED28)))
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#if defined __GNUC__
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// GCC version
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typedef struct port_intctx intctx_t;
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EXTERNC int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK
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// this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655
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// coverity[uninit_use]
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register intctx_t *r13 asm ("r13");
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otp->activeStack = r13;
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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// ISR context
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remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__;
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} else {
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remainingStack = (int)(r13 - 1) - (int)otp->wabase;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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return 99999;
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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}
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#else /* __GNUC__ */
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extern uint32_t CSTACK$$Base; /* symbol created by the IAR linker */
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extern uint32_t IRQSTACK$$Base; /* symbol created by the IAR linker */
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EXTERNC int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)&IRQSTACK$$Base;
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} else {
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remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)otp->p_stklimit;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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return 999999;
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#endif
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}
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// IAR version
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#endif /* GNU / IAR */
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void _unhandled_exception(void) {
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/*lint -restore*/
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|
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chDbgPanic3("_unhandled_exception", __FILE__, __LINE__);
|
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while (true) {
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}
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}
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|
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void DebugMonitorVector(void) {
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chDbgPanic3("DebugMonitorVector", __FILE__, __LINE__);
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while (TRUE)
|
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;
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}
|
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|
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void UsageFaultVector(void) {
|
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chDbgPanic3("UsageFaultVector", __FILE__, __LINE__);
|
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while (TRUE)
|
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;
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}
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|
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void BusFaultVector(void) {
|
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chDbgPanic3("BusFaultVector", __FILE__, __LINE__);
|
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while (TRUE) {
|
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}
|
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}
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|
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/**
|
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+ * @brief Register values for postmortem debugging.
|
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+ */
|
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volatile uint32_t postmortem_r0;
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volatile uint32_t postmortem_r1;
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volatile uint32_t postmortem_r2;
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volatile uint32_t postmortem_r3;
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volatile uint32_t postmortem_r12;
|
||||
volatile uint32_t postmortem_lr; /* Link register. */
|
||||
volatile uint32_t postmortem_pc; /* Program counter. */
|
||||
volatile uint32_t postmortem_psr;/* Program status register. */
|
||||
volatile uint32_t postmortem_CFSR;
|
||||
volatile uint32_t postmortem_HFSR;
|
||||
volatile uint32_t postmortem_DFSR;
|
||||
volatile uint32_t postmortem_AFSR;
|
||||
volatile uint32_t postmortem_BFAR;
|
||||
volatile uint32_t postmortem_MMAR;
|
||||
volatile uint32_t postmortem_SCB_SHCSR;
|
||||
|
||||
/**
|
||||
* @brief Evaluates to TRUE if system runs under debugger control.
|
||||
* @note This bit resets only by power reset.
|
||||
*/
|
||||
#define is_under_debugger() (((CoreDebug)->DHCSR) & \
|
||||
CoreDebug_DHCSR_C_DEBUGEN_Msk)
|
||||
|
||||
/**
|
||||
*
|
||||
*/
|
||||
void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress) {
|
||||
|
||||
postmortem_r0 = pulFaultStackAddress[0];
|
||||
postmortem_r1 = pulFaultStackAddress[1];
|
||||
postmortem_r2 = pulFaultStackAddress[2];
|
||||
postmortem_r3 = pulFaultStackAddress[3];
|
||||
postmortem_r12 = pulFaultStackAddress[4];
|
||||
postmortem_lr = pulFaultStackAddress[5];
|
||||
postmortem_pc = pulFaultStackAddress[6];
|
||||
postmortem_psr = pulFaultStackAddress[7];
|
||||
|
||||
/* Configurable Fault Status Register. Consists of MMSR, BFSR and UFSR */
|
||||
postmortem_CFSR = GET_CFSR();
|
||||
|
||||
/* Hard Fault Status Register */
|
||||
postmortem_HFSR = (*((volatile uint32_t *) (0xE000ED2C)));
|
||||
|
||||
/* Debug Fault Status Register */
|
||||
postmortem_DFSR = (*((volatile uint32_t *) (0xE000ED30)));
|
||||
|
||||
/* Auxiliary Fault Status Register */
|
||||
postmortem_AFSR = (*((volatile uint32_t *) (0xE000ED3C)));
|
||||
|
||||
/* Read the Fault Address Registers. These may not contain valid values.
|
||||
Check BFARVALID/MMARVALID to see if they are valid values
|
||||
MemManage Fault Address Register */
|
||||
postmortem_MMAR = (*((volatile uint32_t *) (0xE000ED34)));
|
||||
/* Bus Fault Address Register */
|
||||
postmortem_BFAR = (*((volatile uint32_t *) (0xE000ED38)));
|
||||
|
||||
postmortem_SCB_SHCSR = SCB->SHCSR;
|
||||
|
||||
if (is_under_debugger()) {
|
||||
__asm("BKPT #0\n");
|
||||
// Break into the debugger
|
||||
}
|
||||
|
||||
/* harmless infinite loop */
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void HardFaultVector(void) {
|
||||
#if 0 && defined __GNUC__
|
||||
__asm volatile (
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, [r0, #24] \n"
|
||||
" ldr r2, handler2_address_const \n"
|
||||
" bx r2 \n"
|
||||
" handler2_address_const: .word prvGetRegistersFromStack \n"
|
||||
);
|
||||
|
||||
#else
|
||||
#endif /* 0 && defined __GNUC__ */
|
||||
|
||||
int cfsr = GET_CFSR();
|
||||
if (cfsr & 0x1) {
|
||||
chDbgPanic3("H IACCVIOL", __FILE__, __LINE__);
|
||||
} else if (cfsr & 0x100) {
|
||||
chDbgPanic3("H IBUSERR", __FILE__, __LINE__);
|
||||
} else if (cfsr & 0x20000) {
|
||||
chDbgPanic3("H INVSTATE", __FILE__, __LINE__);
|
||||
} else {
|
||||
chDbgPanic3("HardFaultVector", __FILE__, __LINE__);
|
||||
}
|
||||
|
||||
while (TRUE) {
|
||||
}
|
||||
}
|
||||
|
||||
#if HAL_USE_SPI
|
||||
bool isSpiInitialized[5] = { false, false, false, false, false };
|
||||
|
||||
static int getSpiAf(SPIDriver *driver) {
|
||||
#if STM32_SPI_USE_SPI1
|
||||
if (driver == &SPID1) {
|
||||
return EFI_SPI1_AF;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI2
|
||||
if (driver == &SPID2) {
|
||||
return EFI_SPI2_AF;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI3
|
||||
if (driver == &SPID3) {
|
||||
return EFI_SPI3_AF;
|
||||
}
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
brain_pin_e getMisoPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1misoPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2misoPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3misoPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
brain_pin_e getMosiPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1mosiPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2mosiPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3mosiPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
brain_pin_e getSckPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1sckPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2sckPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3sckPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
void turnOnSpi(spi_device_e device) {
|
||||
if (isSpiInitialized[device])
|
||||
return; // already initialized
|
||||
isSpiInitialized[device] = true;
|
||||
if (device == SPI_DEVICE_1) {
|
||||
// todo: introduce a nice structure with all fields for same SPI
|
||||
#if STM32_SPI_USE_SPI1
|
||||
// scheduleMsg(&logging, "Turning on SPI1 pins");
|
||||
initSpiModule(&SPID1, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi1SckMode,
|
||||
engineConfiguration->spi1MosiMode,
|
||||
engineConfiguration->spi1MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI1 */
|
||||
}
|
||||
if (device == SPI_DEVICE_2) {
|
||||
#if STM32_SPI_USE_SPI2
|
||||
// scheduleMsg(&logging, "Turning on SPI2 pins");
|
||||
initSpiModule(&SPID2, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi2SckMode,
|
||||
engineConfiguration->spi2MosiMode,
|
||||
engineConfiguration->spi2MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI2 */
|
||||
}
|
||||
if (device == SPI_DEVICE_3) {
|
||||
#if STM32_SPI_USE_SPI3
|
||||
// scheduleMsg(&logging, "Turning on SPI3 pins");
|
||||
initSpiModule(&SPID3, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi3SckMode,
|
||||
engineConfiguration->spi3MosiMode,
|
||||
engineConfiguration->spi3MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI3 */
|
||||
}
|
||||
if (device == SPI_DEVICE_4) {
|
||||
#if STM32_SPI_USE_SPI4
|
||||
// scheduleMsg(&logging, "Turning on SPI4 pins");
|
||||
/* there is no cofiguration fields for SPI4 in engineConfiguration, rely on board init code
|
||||
* it should set proper functions for SPI4 pins */
|
||||
#endif /* STM32_SPI_USE_SPI4 */
|
||||
}
|
||||
}
|
||||
|
||||
void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso,
|
||||
brain_pin_e mosi,
|
||||
int sckMode,
|
||||
int mosiMode,
|
||||
int misoMode) {
|
||||
|
||||
/**
|
||||
* See https://github.com/rusefi/rusefi/pull/664/
|
||||
*
|
||||
* Info on the silicon defect can be found in this document, section 2.5.2:
|
||||
* https://www.st.com/content/ccc/resource/technical/document/errata_sheet/0a/98/58/84/86/b6/47/a2/DM00037591.pdf/files/DM00037591.pdf/jcr:content/translations/en.DM00037591.pdf
|
||||
*/
|
||||
efiSetPadMode("SPI clock", sck, PAL_MODE_ALTERNATE(getSpiAf(driver)) | sckMode | PAL_STM32_OSPEED_HIGHEST);
|
||||
|
||||
efiSetPadMode("SPI master out", mosi, PAL_MODE_ALTERNATE(getSpiAf(driver)) | mosiMode | PAL_STM32_OSPEED_HIGHEST);
|
||||
efiSetPadMode("SPI master in ", miso, PAL_MODE_ALTERNATE(getSpiAf(driver)) | misoMode | PAL_STM32_OSPEED_HIGHEST);
|
||||
}
|
||||
|
||||
void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
|
||||
spiConfig->end_cb = nullptr;
|
||||
ioportid_t port = getHwPort("spi", csPin);
|
||||
ioportmask_t pin = getHwPin("spi", csPin);
|
||||
spiConfig->ssport = port;
|
||||
spiConfig->sspad = pin;
|
||||
efiSetPadMode("chip select", csPin, PAL_STM32_MODE_OUTPUT);
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_SPI */
|
||||
|
||||
#if EFI_CAN_SUPPORT
|
||||
|
||||
static bool isValidCan1RxPin(brain_pin_e pin) {
|
||||
return pin == GPIOA_11 || pin == GPIOB_8 || pin == GPIOD_0;
|
||||
}
|
||||
|
||||
static bool isValidCan1TxPin(brain_pin_e pin) {
|
||||
return pin == GPIOA_12 || pin == GPIOB_9 || pin == GPIOD_1;
|
||||
}
|
||||
|
||||
static bool isValidCan2RxPin(brain_pin_e pin) {
|
||||
return pin == GPIOB_5 || pin == GPIOB_12;
|
||||
}
|
||||
|
||||
static bool isValidCan2TxPin(brain_pin_e pin) {
|
||||
return pin == GPIOB_6 || pin == GPIOB_13;
|
||||
}
|
||||
|
||||
bool isValidCanTxPin(brain_pin_e pin) {
|
||||
return isValidCan1TxPin(pin) || isValidCan2TxPin(pin);
|
||||
}
|
||||
|
||||
bool isValidCanRxPin(brain_pin_e pin) {
|
||||
return isValidCan1RxPin(pin) || isValidCan2RxPin(pin);
|
||||
}
|
||||
|
||||
CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) {
|
||||
#if STM32_CAN_USE_CAN1
|
||||
if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx))
|
||||
return &CAND1;
|
||||
#endif
|
||||
#if STM32_CAN_USE_CAN2
|
||||
if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx))
|
||||
return &CAND2;
|
||||
#endif
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif /* EFI_CAN_SUPPORT */
|
||||
|
||||
size_t flashSectorSize(flashsector_t sector) {
|
||||
// sectors 0..11 are the 1st memory bank (1Mb), and 12..23 are the 2nd (the same structure).
|
||||
|
|
@ -404,6 +25,3 @@ uintptr_t getFlashAddrFirstCopy() {
|
|||
uintptr_t getFlashAddrSecondCopy() {
|
||||
return 0x080C0000;
|
||||
}
|
||||
|
||||
#endif /* EFI_PROD_CODE */
|
||||
|
||||
|
|
|
|||
|
|
@ -5,379 +5,7 @@
|
|||
* @author Andrey Belomutskiy, (c) 2012-2020
|
||||
*/
|
||||
|
||||
#include "global.h"
|
||||
#include "mpu_util.h"
|
||||
#include "flash_int.h"
|
||||
#include "engine.h"
|
||||
#include "pin_repository.h"
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#include "os_util.h"
|
||||
|
||||
EXTERN_ENGINE;
|
||||
|
||||
extern "C" {
|
||||
void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress);
|
||||
}
|
||||
|
||||
extern uint32_t __main_stack_base__;
|
||||
|
||||
#define GET_CFSR() (*((volatile uint32_t *) (0xE000ED28)))
|
||||
|
||||
#if defined __GNUC__
|
||||
// GCC version
|
||||
|
||||
typedef struct port_intctx intctx_t;
|
||||
|
||||
EXTERNC int getRemainingStack(thread_t *otp) {
|
||||
|
||||
#if CH_DBG_ENABLE_STACK_CHECK
|
||||
// this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655
|
||||
// coverity[uninit_use]
|
||||
register intctx_t *r13 asm ("r13");
|
||||
otp->activeStack = r13;
|
||||
|
||||
int remainingStack;
|
||||
if (ch.dbg.isr_cnt > 0) {
|
||||
// ISR context
|
||||
remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__;
|
||||
} else {
|
||||
remainingStack = (int)(r13 - 1) - (int)otp->wabase;
|
||||
}
|
||||
otp->remainingStack = remainingStack;
|
||||
return remainingStack;
|
||||
#else
|
||||
UNUSED(otp);
|
||||
return 99999;
|
||||
#endif /* CH_DBG_ENABLE_STACK_CHECK */
|
||||
}
|
||||
|
||||
#else /* __GNUC__ */
|
||||
|
||||
extern uint32_t CSTACK$$Base; /* symbol created by the IAR linker */
|
||||
extern uint32_t IRQSTACK$$Base; /* symbol created by the IAR linker */
|
||||
|
||||
EXTERNC int getRemainingStack(thread_t *otp) {
|
||||
#if CH_DBG_ENABLE_STACK_CHECK
|
||||
int remainingStack;
|
||||
if (ch.dbg.isr_cnt > 0) {
|
||||
remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)&IRQSTACK$$Base;
|
||||
} else {
|
||||
remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)otp->p_stklimit;
|
||||
}
|
||||
otp->remainingStack = remainingStack;
|
||||
return remainingStack;
|
||||
#else
|
||||
return 999999;
|
||||
#endif
|
||||
}
|
||||
|
||||
// IAR version
|
||||
|
||||
#endif /* GNU / IAR */
|
||||
|
||||
|
||||
void _unhandled_exception(void) {
|
||||
/*lint -restore*/
|
||||
|
||||
chDbgPanic3("_unhandled_exception", __FILE__, __LINE__);
|
||||
while (true) {
|
||||
}
|
||||
}
|
||||
|
||||
void DebugMonitorVector(void) {
|
||||
chDbgPanic3("DebugMonitorVector", __FILE__, __LINE__);
|
||||
while (TRUE)
|
||||
;
|
||||
}
|
||||
|
||||
void UsageFaultVector(void) {
|
||||
chDbgPanic3("UsageFaultVector", __FILE__, __LINE__);
|
||||
while (TRUE)
|
||||
;
|
||||
}
|
||||
|
||||
void BusFaultVector(void) {
|
||||
chDbgPanic3("BusFaultVector", __FILE__, __LINE__);
|
||||
while (TRUE) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
+ * @brief Register values for postmortem debugging.
|
||||
+ */
|
||||
volatile uint32_t postmortem_r0;
|
||||
volatile uint32_t postmortem_r1;
|
||||
volatile uint32_t postmortem_r2;
|
||||
volatile uint32_t postmortem_r3;
|
||||
volatile uint32_t postmortem_r12;
|
||||
volatile uint32_t postmortem_lr; /* Link register. */
|
||||
volatile uint32_t postmortem_pc; /* Program counter. */
|
||||
volatile uint32_t postmortem_psr;/* Program status register. */
|
||||
volatile uint32_t postmortem_CFSR;
|
||||
volatile uint32_t postmortem_HFSR;
|
||||
volatile uint32_t postmortem_DFSR;
|
||||
volatile uint32_t postmortem_AFSR;
|
||||
volatile uint32_t postmortem_BFAR;
|
||||
volatile uint32_t postmortem_MMAR;
|
||||
volatile uint32_t postmortem_SCB_SHCSR;
|
||||
|
||||
/**
|
||||
* @brief Evaluates to TRUE if system runs under debugger control.
|
||||
* @note This bit resets only by power reset.
|
||||
*/
|
||||
#define is_under_debugger() (((CoreDebug)->DHCSR) & \
|
||||
CoreDebug_DHCSR_C_DEBUGEN_Msk)
|
||||
|
||||
/**
|
||||
*
|
||||
*/
|
||||
void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress) {
|
||||
|
||||
postmortem_r0 = pulFaultStackAddress[0];
|
||||
postmortem_r1 = pulFaultStackAddress[1];
|
||||
postmortem_r2 = pulFaultStackAddress[2];
|
||||
postmortem_r3 = pulFaultStackAddress[3];
|
||||
postmortem_r12 = pulFaultStackAddress[4];
|
||||
postmortem_lr = pulFaultStackAddress[5];
|
||||
postmortem_pc = pulFaultStackAddress[6];
|
||||
postmortem_psr = pulFaultStackAddress[7];
|
||||
|
||||
/* Configurable Fault Status Register. Consists of MMSR, BFSR and UFSR */
|
||||
postmortem_CFSR = GET_CFSR();
|
||||
|
||||
/* Hard Fault Status Register */
|
||||
postmortem_HFSR = (*((volatile uint32_t *) (0xE000ED2C)));
|
||||
|
||||
/* Debug Fault Status Register */
|
||||
postmortem_DFSR = (*((volatile uint32_t *) (0xE000ED30)));
|
||||
|
||||
/* Auxiliary Fault Status Register */
|
||||
postmortem_AFSR = (*((volatile uint32_t *) (0xE000ED3C)));
|
||||
|
||||
/* Read the Fault Address Registers. These may not contain valid values.
|
||||
Check BFARVALID/MMARVALID to see if they are valid values
|
||||
MemManage Fault Address Register */
|
||||
postmortem_MMAR = (*((volatile uint32_t *) (0xE000ED34)));
|
||||
/* Bus Fault Address Register */
|
||||
postmortem_BFAR = (*((volatile uint32_t *) (0xE000ED38)));
|
||||
|
||||
postmortem_SCB_SHCSR = SCB->SHCSR;
|
||||
|
||||
if (is_under_debugger()) {
|
||||
__asm("BKPT #0\n");
|
||||
// Break into the debugger
|
||||
}
|
||||
|
||||
/* harmless infinite loop */
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void HardFaultVector(void) {
|
||||
#if 0 && defined __GNUC__
|
||||
__asm volatile (
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, [r0, #24] \n"
|
||||
" ldr r2, handler2_address_const \n"
|
||||
" bx r2 \n"
|
||||
" handler2_address_const: .word prvGetRegistersFromStack \n"
|
||||
);
|
||||
|
||||
#else
|
||||
#endif /* 0 && defined __GNUC__ */
|
||||
|
||||
int cfsr = GET_CFSR();
|
||||
if (cfsr & 0x1) {
|
||||
chDbgPanic3("H IACCVIOL", __FILE__, __LINE__);
|
||||
} else if (cfsr & 0x100) {
|
||||
chDbgPanic3("H IBUSERR", __FILE__, __LINE__);
|
||||
} else if (cfsr & 0x20000) {
|
||||
chDbgPanic3("H INVSTATE", __FILE__, __LINE__);
|
||||
} else {
|
||||
chDbgPanic3("HardFaultVector", __FILE__, __LINE__);
|
||||
}
|
||||
|
||||
while (TRUE) {
|
||||
}
|
||||
}
|
||||
|
||||
#if HAL_USE_SPI
|
||||
bool isSpiInitialized[5] = { false, false, false, false, false };
|
||||
|
||||
static int getSpiAf(SPIDriver *driver) {
|
||||
#if STM32_SPI_USE_SPI1
|
||||
if (driver == &SPID1) {
|
||||
return EFI_SPI1_AF;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI2
|
||||
if (driver == &SPID2) {
|
||||
return EFI_SPI2_AF;
|
||||
}
|
||||
#endif
|
||||
#if STM32_SPI_USE_SPI3
|
||||
if (driver == &SPID3) {
|
||||
return EFI_SPI3_AF;
|
||||
}
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
brain_pin_e getMisoPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1misoPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2misoPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3misoPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
brain_pin_e getMosiPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1mosiPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2mosiPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3mosiPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
brain_pin_e getSckPin(spi_device_e device) {
|
||||
switch(device) {
|
||||
case SPI_DEVICE_1:
|
||||
return CONFIG(spi1sckPin);
|
||||
case SPI_DEVICE_2:
|
||||
return CONFIG(spi2sckPin);
|
||||
case SPI_DEVICE_3:
|
||||
return CONFIG(spi3sckPin);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return GPIO_UNASSIGNED;
|
||||
}
|
||||
|
||||
void turnOnSpi(spi_device_e device) {
|
||||
if (isSpiInitialized[device])
|
||||
return; // already initialized
|
||||
isSpiInitialized[device] = true;
|
||||
if (device == SPI_DEVICE_1) {
|
||||
// todo: introduce a nice structure with all fields for same SPI
|
||||
#if STM32_SPI_USE_SPI1
|
||||
// scheduleMsg(&logging, "Turning on SPI1 pins");
|
||||
initSpiModule(&SPID1, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi1SckMode,
|
||||
engineConfiguration->spi1MosiMode,
|
||||
engineConfiguration->spi1MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI1 */
|
||||
}
|
||||
if (device == SPI_DEVICE_2) {
|
||||
#if STM32_SPI_USE_SPI2
|
||||
// scheduleMsg(&logging, "Turning on SPI2 pins");
|
||||
initSpiModule(&SPID2, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi2SckMode,
|
||||
engineConfiguration->spi2MosiMode,
|
||||
engineConfiguration->spi2MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI2 */
|
||||
}
|
||||
if (device == SPI_DEVICE_3) {
|
||||
#if STM32_SPI_USE_SPI3
|
||||
// scheduleMsg(&logging, "Turning on SPI3 pins");
|
||||
initSpiModule(&SPID3, getSckPin(device),
|
||||
getMisoPin(device),
|
||||
getMosiPin(device),
|
||||
engineConfiguration->spi3SckMode,
|
||||
engineConfiguration->spi3MosiMode,
|
||||
engineConfiguration->spi3MisoMode);
|
||||
#endif /* STM32_SPI_USE_SPI3 */
|
||||
}
|
||||
if (device == SPI_DEVICE_4) {
|
||||
#if STM32_SPI_USE_SPI4
|
||||
// scheduleMsg(&logging, "Turning on SPI4 pins");
|
||||
/* there is no cofiguration fields for SPI4 in engineConfiguration, rely on board init code
|
||||
* it should set proper functions for SPI4 pins */
|
||||
#endif /* STM32_SPI_USE_SPI4 */
|
||||
}
|
||||
}
|
||||
|
||||
void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso,
|
||||
brain_pin_e mosi,
|
||||
int sckMode,
|
||||
int mosiMode,
|
||||
int misoMode) {
|
||||
|
||||
efiSetPadMode("SPI clock", sck, PAL_MODE_ALTERNATE(getSpiAf(driver)) + sckMode);
|
||||
|
||||
efiSetPadMode("SPI master out", mosi, PAL_MODE_ALTERNATE(getSpiAf(driver)) + mosiMode);
|
||||
efiSetPadMode("SPI master in ", miso, PAL_MODE_ALTERNATE(getSpiAf(driver)) + misoMode);
|
||||
}
|
||||
|
||||
void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
|
||||
spiConfig->end_cb = NULL;
|
||||
ioportid_t port = getHwPort("spi", csPin);
|
||||
ioportmask_t pin = getHwPin("spi", csPin);
|
||||
spiConfig->ssport = port;
|
||||
spiConfig->sspad = pin;
|
||||
efiSetPadMode("chip select", csPin, PAL_STM32_MODE_OUTPUT);
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_SPI */
|
||||
|
||||
#if EFI_CAN_SUPPORT
|
||||
|
||||
static bool isValidCan1RxPin(brain_pin_e pin) {
|
||||
return pin == GPIOA_11 || pin == GPIOB_8 || pin == GPIOD_0;
|
||||
}
|
||||
|
||||
static bool isValidCan1TxPin(brain_pin_e pin) {
|
||||
return pin == GPIOA_12 || pin == GPIOB_9 || pin == GPIOD_1;
|
||||
}
|
||||
|
||||
static bool isValidCan2RxPin(brain_pin_e pin) {
|
||||
return pin == GPIOB_5 || pin == GPIOB_12;
|
||||
}
|
||||
|
||||
static bool isValidCan2TxPin(brain_pin_e pin) {
|
||||
return pin == GPIOB_6 || pin == GPIOB_13;
|
||||
}
|
||||
|
||||
bool isValidCanTxPin(brain_pin_e pin) {
|
||||
return isValidCan1TxPin(pin) || isValidCan2TxPin(pin);
|
||||
}
|
||||
|
||||
bool isValidCanRxPin(brain_pin_e pin) {
|
||||
return isValidCan1RxPin(pin) || isValidCan2RxPin(pin);
|
||||
}
|
||||
|
||||
CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) {
|
||||
#if STM32_CAN_USE_CAN1
|
||||
if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx))
|
||||
return &CAND1;
|
||||
#endif
|
||||
#if STM32_CAN_USE_CAN2
|
||||
if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx))
|
||||
return &CAND2;
|
||||
#endif
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif /* EFI_CAN_SUPPORT */
|
||||
|
||||
size_t flashSectorSize(flashsector_t sector) {
|
||||
// sectors 0..11 are the 1st memory bank (1Mb), and 12..23 are the 2nd (the same structure).
|
||||
|
|
|
|||
Loading…
Reference in New Issue