adc: some comments
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@ -40,14 +40,32 @@ inline bool isAdcChannelOffChip(adc_channel_e hwChannel) {
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#if !defined(GPT_FREQ_FAST) || !defined(GPT_PERIOD_FAST)
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#if !defined(GPT_FREQ_FAST) || !defined(GPT_PERIOD_FAST)
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/**
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/*
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* 8000 RPM is 133Hz
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* 8000 RPM is 133Hz
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* If we want to sample MAP once per 5 degrees we need 133Hz * (360 / 5) = 9576Hz of fast ADC
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* If we want to sample MAP once per 5 degrees we need 133Hz * (360 / 5) = 9576Hz of fast ADC ~= 10 KHz
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*/
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*/
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// todo: migrate to continuous ADC mode? probably not - we cannot afford the callback in
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// todo: continuous mode. todo: look into our options
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/*
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#define GPT_FREQ_FAST 100000 /* PWM clock frequency. I wonder what does this setting mean? */
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* TODO: migrate to continuous ADC mode? probably not - we cannot afford the callback in continuous mode.
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#define GPT_PERIOD_FAST 10 /* PWM period (in PWM ticks). */
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* TODO: look into other options
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* TODO: ADC convertion can be triggered directly from timer, with no SW intervention
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*/
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/* PWM clock frequency. Timer clock = 100 KHz */
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#define GPT_FREQ_FAST 100000
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/* PWM period (in PWM ticks), 100 KHz / 10 = 10KHz callback rate */
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#define GPT_PERIOD_FAST 10
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/*
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* We have 1 / (GPT_FREQ_FAST / GPT_PERIOD_FAST) to finish conversion = 100 uS
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* With ADC_SAMPLING_FAST = 28 ADC clock @ 21 MHz (F4) -> one channel conversion takes 1.33(3) uS
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* Oversampling is ADC_BUF_DEPTH_FAST = 4
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* We can do up-to 100 / (1.33(3) * 4) = 18.75 channels conversions
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* So we can enable ALL channels for fast ADC.
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* This will increase bus load with more DMA transfers, but who cares?
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*/
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#endif /* GPT_FREQ_FAST GPT_PERIOD_FAST */
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#endif /* GPT_FREQ_FAST GPT_PERIOD_FAST */
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#if HAL_USE_ADC
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#if HAL_USE_ADC
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