diff --git a/firmware/iar/ch.ewp b/firmware/iar/ch.ewp
index 89927c6d5e..83e12a6f50 100644
--- a/firmware/iar/ch.ewp
+++ b/firmware/iar/ch.ewp
@@ -300,62 +300,62 @@
           <state>$PROJ_DIR$\..\</state>
           <state>$PROJ_DIR$\..\ChibiOS-Contrib\os\hal\include</state>
           <state>$PROJ_DIR$\..\ChibiOS-Contrib\os\various</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\compilers</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\compilers\IAR</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\devices</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\devices\STM32F4xx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\common\startup</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\ext</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\include</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\lib</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\osal</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\osal\rt</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\common</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\common\ARMCMx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\ADCv2</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\CANv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DACv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DMAv2</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\EXTIv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\GPIOv2</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\I2Cv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\OTGv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\RTCv2</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SDIOv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv1</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv2</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\src</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\dox</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\include</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\ports</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\cmsis_os</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\compilers</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\compilers\IAR</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\rt\src</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various\cpp_wrappers</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib\accel</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various\fatfs_bindings</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\various\shell</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx\compilers</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx\compilers\IAR</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx\devices</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx\devices\STM32F4xx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\common\startup</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ext</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\include</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\lib</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\osal</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\osal\rt</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\common</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\common\ARMCMx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\ADCv2</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\CANv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DACv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DMAv2</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\EXTIv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\GPIOv2</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\I2Cv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\OTGv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\RTCv2</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SDIOv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SPIv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv1</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv2</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\src</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\dox</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\include</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\ports</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\cmsis_os</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\compilers</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\compilers\IAR</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\rt\src</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various\cpp_wrappers</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib\accel</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various\fatfs_bindings</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\various\shell</state>
           <state>$PROJ_DIR$\..\controllers</state>
           <state>$PROJ_DIR$\..\controllers\algo</state>
           <state>$PROJ_DIR$\..\controllers\core</state>
@@ -631,8 +631,8 @@
         <option>
           <name>AUserIncludes</name>
           <state>$PROJ_DIR$\..</state>
-          <state>$PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\STM32F4xx</state>
-          <state>$PROJ_DIR$\..\chibios\boards\ST_STM32F4_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ports\IAR\ARMCMx\STM32F4xx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\boards\ST_STM32F4_DISCOVERY</state>
         </option>
         <option>
           <name>AExtraOptionsCheckV2</name>
@@ -1304,24 +1304,24 @@
         <option>
           <name>CCIncludePath2</name>
           <state>$PROJ_DIR$\..\</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F2_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F3_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F3_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F401C_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F401C_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F429I_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F429I_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F4_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F4_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F746G_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32F746G_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32L476_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32L476_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32L_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32L_DISCOVERY\cfg</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM32VL_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM8L_DISCOVERY</state>
-          <state>$PROJ_DIR$\..\ChibiOS\os\hal\boards\ST_STM8S_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F2_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F3_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F3_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F401C_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F401C_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F429I_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F429I_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F4_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F4_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F746G_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32F746G_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32L476_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32L476_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32L_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32L_DISCOVERY\cfg</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM32VL_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM8L_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\hal\boards\ST_STM8S_DISCOVERY</state>
           <state>$PROJ_DIR$\..\config\stm32f4ems</state>
           <state>$PROJ_DIR$\..\..\..\test</state>
         </option>
@@ -1569,8 +1569,8 @@
         <option>
           <name>AUserIncludes</name>
           <state>$PROJ_DIR$\..</state>
-          <state>$PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\STM32F4xx</state>
-          <state>$PROJ_DIR$\..\chibios\boards\ST_STM32F4_DISCOVERY</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\os\ports\IAR\ARMCMx\STM32F4xx</state>
+          <state>$PROJ_DIR$\..\ChibiOS3\boards\ST_STM32F4_DISCOVERY</state>
         </option>
         <option>
           <name>AExtraOptionsCheckV2</name>
@@ -1967,7 +1967,7 @@
               <group>
                 <name>STM32F4xx</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\devices\STM32F4xx\cmparams.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\common\ports\ARMCMx\devices\STM32F4xx\cmparams.h</name>
                 </file>
               </group>
             </group>
@@ -1990,37 +1990,37 @@
           <group>
             <name>include</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\arm_common_tables.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\arm_common_tables.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\arm_const_structs.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\arm_const_structs.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\arm_math.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\arm_math.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cm0.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cm0.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cm0plus.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cm0plus.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cm3.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cm3.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cm4.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cm4.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cm7.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cm7.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cmFunc.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cmFunc.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cmInstr.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cmInstr.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\include\core_cmSimd.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\include\core_cmSimd.h</name>
             </file>
           </group>
           <group>
@@ -2028,61 +2028,61 @@
             <group>
               <name>STM32F4xx</name>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f401xc.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f401xc.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f401xe.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f401xe.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f405xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f405xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f407xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f407xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f410cx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f410cx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f410rx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f410rx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f410tx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f410tx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f411xe.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f411xe.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f415xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f415xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f417xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f417xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f427xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f427xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f429xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f429xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f437xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f437xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f439xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f439xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f446xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f446xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f469xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f469xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f479xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f479xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\stm32f4xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\stm32f4xx.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\ext\CMSIS\ST\STM32F4xx\system_stm32f4xx.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\ext\CMSIS\ST\STM32F4xx\system_stm32f4xx.h</name>
               </file>
             </group>
           </group>
@@ -2096,97 +2096,97 @@
         <group>
           <name>include</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\adc.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\adc.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\can.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\can.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\dac.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\dac.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\ext.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\ext.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\gpt.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\gpt.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_buffers.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_buffers.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_channels.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_channels.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_files.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_files.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_ioblock.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_ioblock.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_mmcsd.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_mmcsd.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_queues.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_queues.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\hal_streams.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\hal_streams.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\i2c.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\i2c.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\i2s.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\i2s.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\icu.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\icu.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\mac.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\mac.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\mii.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\mii.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\mmc_spi.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\mmc_spi.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\pal.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\pal.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\pwm.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\pwm.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\rtc.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\rtc.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\sdc.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\sdc.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\serial.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\serial.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\serial_usb.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\serial_usb.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\spi.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\spi.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\st.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\st.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\uart.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\uart.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\usb.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\usb.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\usb_cdc.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\usb_cdc.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\include\wdg.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\include\wdg.h</name>
           </file>
         </group>
         <group>
@@ -2194,22 +2194,22 @@
           <group>
             <name>streams</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\chprintf.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\chprintf.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\chprintf.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\chprintf.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\memstreams.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\memstreams.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\memstreams.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\memstreams.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\nullstreams.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\nullstreams.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\nullstreams.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\lib\streams\nullstreams.h</name>
             </file>
           </group>
         </group>
@@ -2218,10 +2218,10 @@
           <group>
             <name>rt</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\osal\rt\osal.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\osal\rt\osal.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\hal\osal\rt\osal.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\hal\osal\rt\osal.h</name>
             </file>
           </group>
         </group>
@@ -2232,13 +2232,13 @@
             <group>
               <name>ARMCMx</name>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\common\ARMCMx\mpu.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\common\ARMCMx\mpu.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\common\ARMCMx\nvic.c</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\common\ARMCMx\nvic.c</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\common\ARMCMx\nvic.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\common\ARMCMx\nvic.h</name>
               </file>
             </group>
           </group>
@@ -2249,179 +2249,179 @@
               <group>
                 <name>ADCv2</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\ADCv2\adc_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\ADCv2\adc_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\ADCv2\adc_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\ADCv2\adc_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>CANv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\CANv1\can_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\CANv1\can_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\CANv1\can_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\CANv1\can_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>DACv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DACv1\dac_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DACv1\dac_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DACv1\dac_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DACv1\dac_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>DMAv2</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DMAv2\stm32_dma.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DMAv2\stm32_dma.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DMAv2\stm32_dma.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\DMAv2\stm32_dma.h</name>
                 </file>
               </group>
               <group>
                 <name>EXTIv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\EXTIv1\ext_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\EXTIv1\ext_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\EXTIv1\ext_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\EXTIv1\ext_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>GPIOv2</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>I2Cv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>OTGv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\OTGv1\stm32_otg.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\OTGv1\stm32_otg.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\OTGv1\usb_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\OTGv1\usb_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\OTGv1\usb_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\OTGv1\usb_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>RTCv2</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>SDIOv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SDIOv1\sdc_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SDIOv1\sdc_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SDIOv1\sdc_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SDIOv1\sdc_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>SPIv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv1\spi_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SPIv1\spi_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv1\spi_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\SPIv1\spi_lld.h</name>
                 </file>
               </group>
               <group>
                 <name>TIMv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\icu_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\icu_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\icu_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\icu_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\st_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\st_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\st_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\st_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\stm32_tim.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\TIMv1\stm32_tim.h</name>
                 </file>
               </group>
               <group>
                 <name>USARTv1</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv1\serial_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv1\serial_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv1\serial_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv1\serial_lld.h</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv1\uart_lld.c</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv1\uart_lld.c</name>
                 </file>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv1\uart_lld.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\LLD\USARTv1\uart_lld.h</name>
                 </file>
               </group>
             </group>
             <group>
               <name>STM32F4xx</name>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.c</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.c</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\hal_lld.c</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\hal_lld.c</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\hal_lld.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\hal_lld.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\stm32_isr.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\stm32_isr.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\stm32_rcc.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\stm32_rcc.h</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F4xx\stm32_registry.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\hal\ports\STM32\STM32F4xx\stm32_registry.h</name>
               </file>
             </group>
           </group>
@@ -2429,79 +2429,79 @@
         <group>
           <name>src</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\adc.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\adc.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\can.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\can.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\dac.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\dac.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\ext.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\ext.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\gpt.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\gpt.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\hal.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\hal.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\hal_buffers.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\hal_buffers.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\hal_mmcsd.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\hal_mmcsd.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\hal_queues.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\hal_queues.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\i2c.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\i2c.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\i2s.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\i2s.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\icu.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\icu.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\mac.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\mac.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\mmc_spi.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\mmc_spi.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\pal.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\pal.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\pwm.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\pwm.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\rtc.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\rtc.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\sdc.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\sdc.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\serial.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\serial.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\serial_usb.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\serial_usb.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\spi.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\spi.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\st.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\st.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\uart.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\uart.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\usb.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\usb.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\hal\src\wdg.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\hal\src\wdg.c</name>
           </file>
         </group>
       </group>
@@ -2513,79 +2513,79 @@
         <group>
           <name>include</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\ch.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\ch.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chbsem.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chbsem.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chcond.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chcond.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chcustomer.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chcustomer.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chdebug.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chdebug.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chdynamic.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chdynamic.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chevents.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chevents.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chheap.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chheap.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chlicense.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chlicense.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chmboxes.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chmboxes.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chmemcore.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chmemcore.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chmempools.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chmempools.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chmsg.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chmsg.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chmtx.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chmtx.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chqueues.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chqueues.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chregistry.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chregistry.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chschd.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chschd.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chsem.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chsem.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chstats.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chstats.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chstreams.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chstreams.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chsys.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chsys.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chsystypes.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chsystypes.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chthreads.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chthreads.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chtm.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chtm.h</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\include\chvt.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\include\chvt.h</name>
           </file>
         </group>
         <group>
@@ -2595,10 +2595,10 @@
             <group>
               <name>cmsis_os</name>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\cmsis_os\cmsis_os.c</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\cmsis_os\cmsis_os.c</name>
               </file>
               <file>
-                <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\cmsis_os\cmsis_os.h</name>
+                <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\cmsis_os\cmsis_os.h</name>
               </file>
             </group>
             <group>
@@ -2606,91 +2606,91 @@
               <group>
                 <name>IAR</name>
                 <file>
-                  <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\compilers\IAR\chtypes.h</name>
+                  <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\compilers\IAR\chtypes.h</name>
                 </file>
               </group>
             </group>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore_timer.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore_timer.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore_v6m.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore_v6m.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore_v6m.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore_v6m.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore_v7m.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore_v7m.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\rt\ports\ARMCMx\chcore_v7m.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\rt\ports\ARMCMx\chcore_v7m.h</name>
             </file>
           </group>
         </group>
         <group>
           <name>src</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chcond.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chcond.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chdebug.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chdebug.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chdynamic.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chdynamic.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chevents.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chevents.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chheap.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chheap.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chmboxes.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chmboxes.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chmemcore.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chmemcore.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chmempools.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chmempools.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chmsg.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chmsg.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chmtx.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chmtx.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chqueues.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chqueues.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chregistry.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chregistry.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chschd.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chschd.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chsem.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chsem.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chstats.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chstats.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chsys.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chsys.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chthreads.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chthreads.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chtm.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chtm.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\rt\src\chvt.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\rt\src\chvt.c</name>
           </file>
         </group>
       </group>
@@ -2699,10 +2699,10 @@
         <group>
           <name>cpp_wrappers</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\cpp_wrappers\ch.cpp</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\cpp_wrappers\ch.cpp</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\cpp_wrappers\syscalls_cpp.cpp</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\cpp_wrappers\syscalls_cpp.cpp</name>
           </file>
         </group>
         <group>
@@ -2710,29 +2710,29 @@
           <group>
             <name>accel</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib\accel\lis302dl.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib\accel\lis302dl.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib\accel\lis302dl.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib\accel\lis302dl.h</name>
             </file>
           </group>
           <group>
             <name>lcd</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib\lcd\lcd3310.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib\lcd\lcd3310.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\devices_lib\lcd\lcd3310.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\devices_lib\lcd\lcd3310.h</name>
             </file>
           </group>
         </group>
         <group>
           <name>fatfs_bindings</name>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\fatfs_bindings\fatfs_diskio.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\fatfs_bindings\fatfs_diskio.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\fatfs_bindings\fatfs_syscall.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\fatfs_bindings\fatfs_syscall.c</name>
           </file>
         </group>
         <group>
@@ -2740,42 +2740,42 @@
           <group>
             <name>arch</name>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\arch\cc.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\arch\cc.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\arch\perf.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\arch\perf.h</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\arch\sys_arch.c</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\arch\sys_arch.c</name>
             </file>
             <file>
-              <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\arch\sys_arch.h</name>
+              <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\arch\sys_arch.h</name>
             </file>
           </group>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\lwipthread.c</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\lwipthread.c</name>
           </file>
           <file>
-            <name>$PROJ_DIR$\..\ChibiOS\os\various\lwip_bindings\lwipthread.h</name>
+            <name>$PROJ_DIR$\..\ChibiOS3\os\various\lwip_bindings\lwipthread.h</name>
           </file>
         </group>
         <group>
           <name>shell</name>
         </group>
         <file>
-          <name>$PROJ_DIR$\..\ChibiOS\os\various\evtimer.c</name>
+          <name>$PROJ_DIR$\..\ChibiOS3\os\various\evtimer.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\ChibiOS\os\various\evtimer.h</name>
+          <name>$PROJ_DIR$\..\ChibiOS3\os\various\evtimer.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\ChibiOS\os\various\shell.c</name>
+          <name>$PROJ_DIR$\..\ChibiOS3\os\various\shell.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\ChibiOS\os\various\shell.h</name>
+          <name>$PROJ_DIR$\..\ChibiOS3\os\various\shell.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\ChibiOS\os\various\syscalls.c</name>
+          <name>$PROJ_DIR$\..\ChibiOS3\os\various\syscalls.c</name>
         </file>
       </group>
     </group>