From 526b4199e6c8bfdd41b93e55c43da79afce8be2c Mon Sep 17 00:00:00 2001 From: sbtoonz <67915879+sbtoonz@users.noreply.github.com> Date: Mon, 30 May 2022 13:48:15 -0500 Subject: [PATCH] Add New Board to compilation output (#4215) * adding my board Signed-off-by: sbtoonz * Add header file to finalize compilation of custom board..how are these hashes calculated? Signed-off-by: sbtoonz * This shouldn't exist in master Signed-off-by: sbtoonz * First refactor of yml Signed-off-by: sbtoonz * Cleanup board_configuration.cpp Signed-off-by: sbtoonz * yml refactor again based on @rusefi 's request Signed-off-by: sbtoonz * remove connector image temporarily while I populate yml with coordinates Signed-off-by: sbtoonz --- firmware/config/boards/48way/board.h | 1019 +++++++++++++++++ firmware/config/boards/48way/board.mk | 9 + .../boards/48way/board_configuration.cpp | 101 ++ .../config/boards/48way/compile_48way.bat | 3 + firmware/config/boards/48way/compile_48way.sh | 3 + .../connectors/generated_ts_name_by_pin.cpp | 47 + .../config/boards/48way/connectors/main.yaml | 106 ++ firmware/config/boards/48way/prepend.txt | 13 + .../controllers/generated/signature_48way.h | 6 + 9 files changed, 1307 insertions(+) create mode 100755 firmware/config/boards/48way/board.h create mode 100755 firmware/config/boards/48way/board.mk create mode 100755 firmware/config/boards/48way/board_configuration.cpp create mode 100755 firmware/config/boards/48way/compile_48way.bat create mode 100755 firmware/config/boards/48way/compile_48way.sh create mode 100755 firmware/config/boards/48way/connectors/generated_ts_name_by_pin.cpp create mode 100755 firmware/config/boards/48way/connectors/main.yaml create mode 100755 firmware/config/boards/48way/prepend.txt create mode 100644 firmware/controllers/generated/signature_48way.h diff --git a/firmware/config/boards/48way/board.h b/firmware/config/boards/48way/board.h new file mode 100755 index 0000000000..dc20bbc548 --- /dev/null +++ b/firmware/config/boards/48way/board.h @@ -0,0 +1,1019 @@ +/** + * @file boards/core8/board.h + * + * @author Ben Brazdziunas, 2022 + */ + +#define BOARD_NAME "48Way" + +#ifndef BOARD_IO_H +#define BOARD_IO_H + +#undef EFI_RTC +#define EFI_RTC TRUE + +#undef EFI_USB_SERIAL +#define EFI_USB_SERIAL TRUE + +#undef EFI_USB_AF +#define EFI_USB_AF 10U + +#undef EFI_USB_SERIAL_DM +#define EFI_USB_SERIAL_DM Gpio::A11 + +#undef EFI_USB_SERIAL_DP +#define EFI_USB_SERIAL_DP Gpio::A12 + +#undef STM32_SERIAL_USE_USART1 +#define STM32_SERIAL_USE_USART1 FALSE + +#undef STM32_UART_USE_USART1 +#define STM32_UART_USE_USART1 TRUE + +#undef TS_PRIMARY_PORT +#define TS_PRIMARY_PORT UARTD1 + +#undef EFI_CONSOLE_TX_BRAIN_PIN +#define EFI_CONSOLE_TX_BRAIN_PIN Gpio::A9 + +#undef EFI_CONSOLE_RX_BRAIN_PIN +#define EFI_CONSOLE_RX_BRAIN_PIN Gpio::A10 + +#undef EFI_USE_OSC +#define EFI_USE_OSC TRUE + +#undef EFI_CAN_SUPPORT +#define EFI_CAN_SUPPORT TRUE + +#undef EFI_FILE_LOGGING +#define EFI_FILE_LOGGING TRUE + +#undef EFI_SDC_DEVICE +#define EFI_SDC_DEVICE SDCD1 + +// #undef HAL_USE_USB_MSD +// #define HAL_USE_USB_MSD FALSE + +#undef EFI_ICU_INPUTS +#define EFI_ICU_INPUTS FALSE + +#undef HAL_TRIGGER_USE_PAL +#define HAL_TRIGGER_USE_PAL TRUE + +#undef EFI_LOGIC_ANALYZER +#define EFI_LOGIC_ANALYZER FALSE + +#undef HAL_VSS_USE_PAL +#define HAL_VSS_USE_PAL TRUE + +#undef LED_CRITICAL_ERROR_BRAIN_PIN +#define LED_CRITICAL_ERROR_BRAIN_PIN Gpio::C11 + +// Ignore USB VBUS pin (we're never a host, only a device) +#define BOARD_OTG_NOVBUSSENS TRUE + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n)*2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n)*2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n)*2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) + +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOB setup: + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 9U) | \ + PIN_AFIO_AF(6, 9U) | \ + PIN_AFIO_AF(7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOC setup: + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_ALTERNATE(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 12U) | \ + PIN_AFIO_AF(9, 12U) | \ + PIN_AFIO_AF(10, 12U) | \ + PIN_AFIO_AF(11, 12U) | \ + PIN_AFIO_AF(12, 12U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOD setup: + */ + +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(0) | \ + PIN_MODE_ALTERNATE(1) | \ + PIN_MODE_ALTERNATE(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOD_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 9U) | \ + PIN_AFIO_AF(1, 9U) | \ + PIN_AFIO_AF(2, 12U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOE setup: + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOE_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOF setup: + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOF_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOG setup: + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOG_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOH setup: + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOH_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +/* + * GPIOI setup: + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(0) | \ + PIN_OSPEED_HIGH(1) | \ + PIN_OSPEED_HIGH(2) | \ + PIN_OSPEED_HIGH(3) | \ + PIN_OSPEED_HIGH(4) | \ + PIN_OSPEED_HIGH(5) | \ + PIN_OSPEED_HIGH(6) | \ + PIN_OSPEED_HIGH(7) | \ + PIN_OSPEED_HIGH(8) | \ + PIN_OSPEED_HIGH(9) | \ + PIN_OSPEED_HIGH(10) | \ + PIN_OSPEED_HIGH(11) | \ + PIN_OSPEED_HIGH(12) | \ + PIN_OSPEED_HIGH(13) | \ + PIN_OSPEED_HIGH(14) | \ + PIN_OSPEED_HIGH(15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_PULLDOWN(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOI_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(0, 0U) | \ + PIN_AFIO_AF(1, 0U) | \ + PIN_AFIO_AF(2, 0U) | \ + PIN_AFIO_AF(3, 0U) | \ + PIN_AFIO_AF(4, 0U) | \ + PIN_AFIO_AF(5, 0U) | \ + PIN_AFIO_AF(6, 0U) | \ + PIN_AFIO_AF(7, 0U)) + +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(8, 0U) | \ + PIN_AFIO_AF(9, 0U) | \ + PIN_AFIO_AF(10, 0U) | \ + PIN_AFIO_AF(11, 0U) | \ + PIN_AFIO_AF(12, 0U) | \ + PIN_AFIO_AF(13, 0U) | \ + PIN_AFIO_AF(14, 0U) | \ + PIN_AFIO_AF(15, 0U)) + +#endif /* BOARD_IO_H */ \ No newline at end of file diff --git a/firmware/config/boards/48way/board.mk b/firmware/config/boards/48way/board.mk new file mode 100755 index 0000000000..197c460a66 --- /dev/null +++ b/firmware/config/boards/48way/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDCPPSRC = $(PROJECT_DIR)/config/boards/48way/board_configuration.cpp + +BOARDINC = $(PROJECT_DIR)/config/boards/48way + +# Override DEFAULT_ENGINE_TYPE +DDEFS += -DSHORT_BOARD_NAME=48way +DDEFS += -DFIRMWARE_ID=\"48way\" +DDEFS += -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS diff --git a/firmware/config/boards/48way/board_configuration.cpp b/firmware/config/boards/48way/board_configuration.cpp new file mode 100755 index 0000000000..d20c69f4ed --- /dev/null +++ b/firmware/config/boards/48way/board_configuration.cpp @@ -0,0 +1,101 @@ +/** + * @file boards/48way/board_configuration.cpp + * + * @brief Configuration defaults for the 48way STM32 board + * + * @author Ben Brazdziunas, 2022 + */ + +#include "pch.h" + +static void setInjectorPins() { + engineConfiguration->injectionPinMode = OM_DEFAULT; + + engineConfiguration->injectionPins[0] = Gpio::E15; + engineConfiguration->injectionPins[1] = Gpio::E14; + engineConfiguration->injectionPins[2] = Gpio::E13; + engineConfiguration->injectionPins[3] = Gpio::E12; + engineConfiguration->injectionPins[4] = Gpio::E11; + engineConfiguration->injectionPins[5] = Gpio::E10; + engineConfiguration->injectionPins[6] = Gpio::E9; + engineConfiguration->injectionPins[7] = Gpio::E8; +} + +static void setIgnitionPins() { + engineConfiguration->ignitionPinMode = OM_DEFAULT; + + engineConfiguration->ignitionPins[0] = Gpio::D12; + engineConfiguration->ignitionPins[1] = Gpio::D13; + engineConfiguration->ignitionPins[2] = Gpio::B15; + engineConfiguration->ignitionPins[3] = Gpio::B14; + engineConfiguration->ignitionPins[4] = Gpio::D8; + engineConfiguration->ignitionPins[5] = Gpio::D9; + engineConfiguration->ignitionPins[6] = Gpio::D11; + engineConfiguration->ignitionPins[7] = Gpio::D10; +} + + +void setSdCardConfigurationOverrides(void) { +} + +static void setEtbConfig() { + +} + +static void setupVbatt() { + // 5.6k high side/10k low side = 1.56 ratio divider + engineConfiguration->analogInputDividerCoefficient = 1.56f; + + // 6.34k high side/ 1k low side + engineConfiguration->vbattDividerCoeff = (6.34 + 1) / 1; + + // Battery sense on PA7 + engineConfiguration->vbattAdcChannel = EFI_ADC_0; + + engineConfiguration->adcVcc = 3.3f; +} + +static void setStepperConfig() { + engineConfiguration->idle.stepperDirectionPin = Gpio::C9; + engineConfiguration->idle.stepperStepPin = Gpio::C8; + engineConfiguration->stepperEnablePin = Gpio::A8; +} + +void setBoardConfigOverrides() { + setupVbatt(); + //setEtbConfig(); + setStepperConfig(); + + // PE3 is error LED, configured in board.mk + engineConfiguration->communicationLedPin = Gpio::Unassigned; + engineConfiguration->runningLedPin = Gpio::C10; + engineConfiguration->warningLedPin = Gpio::Unassigned; + + engineConfiguration->clt.config.bias_resistor = 2490; + engineConfiguration->iat.config.bias_resistor = 2490; + + //CAN 1 bus overwrites + engineConfiguration->canRxPin = Gpio::D0; + engineConfiguration->canTxPin = Gpio::D1; + + //CAN 2 bus overwrites + engineConfiguration->can2RxPin = Gpio::B12; + engineConfiguration->can2TxPin = Gpio::B13; +} + +static void setupDefaultSensorInputs() { + + engineConfiguration->afr.hwChannel = EFI_ADC_4; + setEgoSensor(ES_14Point7_Free); + + engineConfiguration->baroSensor.hwChannel = EFI_ADC_9; + +} + +void setBoardDefaultConfiguration(void) { + setInjectorPins(); + setIgnitionPins(); + engineConfiguration->isSdCardEnabled = false; + engineConfiguration->canBaudRate = B500KBPS; + engineConfiguration->can2BaudRate = B500KBPS; +} diff --git a/firmware/config/boards/48way/compile_48way.bat b/firmware/config/boards/48way/compile_48way.bat new file mode 100755 index 0000000000..2c00196af2 --- /dev/null +++ b/firmware/config/boards/48way/compile_48way.bat @@ -0,0 +1,3 @@ +@echo off + +bash.exe compile_48way.sh diff --git a/firmware/config/boards/48way/compile_48way.sh b/firmware/config/boards/48way/compile_48way.sh new file mode 100755 index 0000000000..624e0b6300 --- /dev/null +++ b/firmware/config/boards/48way/compile_48way.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +bash ../common_make.sh 48way ARCH_STM32F4 \ No newline at end of file diff --git a/firmware/config/boards/48way/connectors/generated_ts_name_by_pin.cpp b/firmware/config/boards/48way/connectors/generated_ts_name_by_pin.cpp new file mode 100755 index 0000000000..cfaa1bf761 --- /dev/null +++ b/firmware/config/boards/48way/connectors/generated_ts_name_by_pin.cpp @@ -0,0 +1,47 @@ +// auto-generated by PinoutLogic.java + +#include "pch.h" + +const char * getBoardSpecificPinName(brain_pin_e brainPin) { + switch(brainPin) { + default: return nullptr; + case Gpio::E2: return "Fan Relay (E2)"; + case Gpio::E3: return "Fuel Relay (E3)"; + case Gpio::E4: return "Launch Control (E4)"; + case Gpio::E5: return "Tachometer (E5)"; + case Gpio::E6: return "Camshaft Input (E6)"; + case Gpio::A0: return "Battery Reference Input (A0)"; + case Gpio::A1: return "TPS Reference Input (A1)"; + case Gpio::A2: return "CLT Reference Input (A2)"; + case Gpio::A3: return "IAT Reference Input (A3)"; + case Gpio::A4: return "O2 Reference Input (A4)"; + case Gpio::C4: return "Fuel Pressure Reference Input (C4)"; + case Gpio::C5: return "Oil Pressure Reference Input (C5)"; + case Gpio::B0: return "MAP Pressure Reference Input (B0)"; + case Gpio::B1: return "BARO Pressure Reference Input (B1)"; + case Gpio::E8: return "Injector 8 Output (E8)"; + case Gpio::E9: return "Injector 7 Output (E9)"; + case Gpio::E10: return "Injector 6 Output (E10)"; + case Gpio::E11: return "Injector 5 Output (E11)"; + case Gpio::E12: return "Injector 4 Output (E12)"; + case Gpio::E13: return "Injector 3 Output (E13)"; + case Gpio::E14: return "Injector 2 Output (E14)"; + case Gpio::E15: return "Injector 1 Output (E15)"; + case Gpio::E1: return "Clutch Input (E1)"; + case Gpio::C7: return "Boost Controller Output (C7)"; + case Gpio::C6: return "IDLE Controller Output (C6)"; + case Gpio::D15: return "HC1 Controller Output (D15)"; + case Gpio::D14: return "HC2 Controller Output (D14)"; + case Gpio::D13: return "Ignition 2 Output (D13)"; + case Gpio::D12: return "Ignition 1 Output (D12)"; + case Gpio::D11: return "Ignition 7 Output (D11)"; + case Gpio::D10: return "Ignition 8 Output (D10)"; + case Gpio::D9: return "Ignition 6 Output (D9)"; + case Gpio::D8: return "Ignition 5 Output (D8)"; + case Gpio::B15: return "Ignition 3 Output (B15)"; + case Gpio::B14: return "Ignition 4 Output (B14)"; + case Gpio::B13: return "CANTX Output (B13)"; + case Gpio::B12: return "CANRX Output (B12)"; + } + return nullptr; +} diff --git a/firmware/config/boards/48way/connectors/main.yaml b/firmware/config/boards/48way/connectors/main.yaml new file mode 100755 index 0000000000..859d2c1489 --- /dev/null +++ b/firmware/config/boards/48way/connectors/main.yaml @@ -0,0 +1,106 @@ +pins: + - id: E2 + class: outputs + ts_name: Fan Relay (E2) + - id: E3 + class: outputs + ts_name: Fuel Relay (E3) + - id: E4 + class: switch_inputs + ts_name: Launch Control (E4) + - id: E5 + class: outputs + ts_name: Tachometer (E5) + - id: [E6, E6] + class: [switch_inputs, event_inputs] + ts_name: Camshaft Input (E6) + - id: EFI_ADC_0 + class: analog_inputs + ts_name: Battery Reference Input (A0) + - id: [A1, EFI_ADC_1] + class: [switch_inputs, analog_inputs] + ts_name: TPS Reference Input (A1) + - id: EFI_ADC_2 + class: analog_inputs + ts_name: CLT Reference Input (A2) + - id: EFI_ADC_3 + class: analog_inputs + ts_name: IAT Reference Input (A3) + - id: EFI_ADC_4 + class: analog_inputs + ts_name: O2 Reference Input (A4) + - id: EFI_ADC_14 + class: analog_inputs + ts_name: Fuel Pressure Reference Input (C4) + - id: EFI_ADC_15 + class: analog_inputs + ts_name: Oil Pressure Reference Input (C5) + - id: EFI_ADC_8 + class: analog_inputs + ts_name: MAP Pressure Reference Input (B0) + - id: EFI_ADC_9 + class: analog_inputs + ts_name: BARO Pressure Reference Input (B1) + - id: E8 + class: outputs + ts_name: Injector 8 Output (E8) + - id: E9 + class: outputs + ts_name: Injector 7 Output (E9) + - id: E10 + class: outputs + ts_name: Injector 6 Output (E10) + - id: E11 + class: outputs + ts_name: Injector 5 Output (E11) + - id: E12 + class: outputs + ts_name: Injector 4 Output (E12) + - id: E13 + class: outputs + ts_name: Injector 3 Output (E13) + - id: E14 + class: outputs + ts_name: Injector 2 Output (E14) + - id: E15 + class: outputs + ts_name: Injector 1 Output (E15) + - id: E1 + class: analog_inputs + ts_name: Clutch Input (E1) + - id: C7 + class: outputs + ts_name: Boost Controller Output (C7) + - id: C6: + class: outputs + ts_name: Idle1 Output (C6) + - id: D15 + class: outputs + ts_name: HC1 Output (D15) + - id: D14 + class: outputs + ts_name: HC2 Output (D14) + - id: D13 + class: outputs + ts_name: Ignition 2 Output (D13) + - id: D12 + class: outputs + ts_name: Ignition 1 Output (D12) + - id: D11 + class: outputs + ts_name: Ignition 7 Output (D11) + - id: D10 + class: outputs + ts_name: Ignition 8 Output (D10) + - id: D9 + class: outputs + ts_name: Ignition 6 Output (D9) + - id: D8 + class: outputs + ts_name: Ignition 5 Output (D8) + - id: B15 + class: outputs + ts_name: Ignition 3 Output (B15) + - id: B14 + class: outputs + ts_name: Ignition 4 Output (B14) diff --git a/firmware/config/boards/48way/prepend.txt b/firmware/config/boards/48way/prepend.txt new file mode 100755 index 0000000000..abb089862b --- /dev/null +++ b/firmware/config/boards/48way/prepend.txt @@ -0,0 +1,13 @@ +#define ts_show_hip9011 false +#define ts_show_cj125 false + +#define ts_show_lcd false +#define ts_show_joystick false +#define ts_show_gps false +#define ts_show_software_knock true + +#define show_test_presets true +#define show_microRusEFI_presets false +#define show_Frankenso_presets false +#define show_Hellen_presets false +#define show_Proteus_presets false \ No newline at end of file diff --git a/firmware/controllers/generated/signature_48way.h b/firmware/controllers/generated/signature_48way.h new file mode 100644 index 0000000000..dc2e7ad4d5 --- /dev/null +++ b/firmware/controllers/generated/signature_48way.h @@ -0,0 +1,6 @@ +// +// was generated automatically by rusEFI tool ConfigDefinition.jar based on gen_config.sh null +// + +#define SIGNATURE_HASH 1757397598 +#define TS_SIGNATURE "rusEFI 2022.05.30.48way.1757397598"