andreika-git
/
rusefi
mirror of https://github.com/andreika-git/rusefi.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Chibi os 20 (#2212) 

* Update ChibiOS

* Fix Makefiles includes paths

* halconf.h: remove flash hack

* mcuconf: fix EXTI ptiorityes

* Digital Input: ICU: use designated initializers, initialize 'arr'

* ChibiOS: lis302dl fix

* ADC: update to new API

* UARTConfig: timeout_cb field, formating

* ChibiOS: remove _exit, _kill, _getpid

* Fix lis302dl

* Bump config versions

* chconfig_common: cosmetic changes

* stm32f4ems: commulative config update

* Update Simulator

* ALLCSRC already contain all needed ChibiOS files.

Same for ALLINC and ALLCPPSRC

* ChibiOS fix for Simulator

* ChibiOS: port lock/unlock hook and MMC over SPI timeout

* STM32F7: update configs

* STM32F7: update linker file

* Cypress: port ADC lld to ChibiOS-20

* Cypress: port SPI lld to ChibiOS-20

* Cypress: port CAN lld to ChibiOS-20

* Cypress: fix include path for rules.ld

* Cypress: update chconf.h and halconf.h for ChibiOS-20

* Kinetis: update ADC lld to ChibiOS-20

* Kinetis: update SPI lld to ChibiOS-20

* Kinetis: update UART lld driver for ChibiOS-20

* Kinetis: update chconf.h and halconf.h for ChibiOS-20

* Kinetis: fix include path for rules.ld

* Nucleo F746: update ld script

* Nucleo F746: fix compile

* Bootloader: fix compilation with ChibiOS-20, cleanup

* Bootloader: add way to pass crosscompiler using CROSS_COMPILE

* Debug build arguments

* Simulator: fix windows compilation

Exclude syscalls_cpp.cpp from compilation
This commit is contained in:
Andrey G 2021-01-19 23:20:35 +03:00 committed by GitHub
parent 20f05fd450
commit 777979c3ca
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
39 changed files with 800 additions and 826 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
firmware/ChibiOS

@ -1 +1 @@
Subproject commit 1a2c5967dc813bdbf1cc7eabfea8377340c8a29e
Subproject commit 0b4897475aceea4ae791f104297d334911a5adf7

2
firmware/ChibiOS-Contrib

@ -1 +1 @@
Subproject commit 8f7c2d187bbb02915f44b926c7aa02185402aef7
Subproject commit 61baa6b036138c155f7cfc5646d833d9423f3243

11
firmware/Makefile
View File

@ -4,7 +4,7 @@
#
CHIBIOS = ChibiOS
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
RULESFILE = $(RULESPATH)/rules.mk
include rusefi_rules.mk
@ -161,12 +161,12 @@ include $(CPU_STARTUP_DIR)
# HAL-OSAL files (optional).
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
include $(CPU_PLATFORM_DIR)
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# EX files (optional).
include $(CHIBIOS)/os/ex/ST/lis302dl.mk
include $(CHIBIOS)/os/ex/devices/ST/lis302dl.mk
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk
@ -205,6 +205,11 @@ ifeq ($(LDSCRIPT),)
LDSCRIPT= config/stm32f4ems/STM32F407xG.ld
endif
$(info PROJECT_BOARD: $(PROJECT_BOARD))
$(info PROJECT_CPU: $(PROJECT_CPU))
$(info CONFDIR: $(CONFDIR))
$(info LDSCRIPT: $(LDSCRIPT))
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \

43
firmware/bootloader/src/Makefile
View File

@ -125,23 +125,28 @@ PROJECT_DIR = ..
CHIBIOS = $(PROJECT_DIR)/ChibiOS
CHIBIOS_CONTRIB = $(PROJECT_DIR)/ChibiOS-Contrib
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
RULESFILE = $(RULESPATH)/rules.mk
include $(PROJECT_DIR)/rusefi.mk
CONFIG = $(PROJECT_DIR)/config
# Include various ChibiOS mk files
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/$(CPU_STARTUP)
# HAL-OSAL files (optional).
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/$(CPU_PLATFORM)
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk
# EX files (optional).
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
include $(CONFIG)/boards/$(PROJECT_BOARD)/board.mk
include $(PROJECT_DIR)/init/init.mk
@ -158,16 +163,8 @@ endif
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(STARTUPSRC) \
$(KERNSRC) \
$(PORTSRC) \
$(OSALSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
CSRC = $(ALLCSRC) \
$(CHIBIOS)/os/various/syscalls.c \
$(CHIBIOS)/os/hal/lib/streams/memstreams.c \
$(CHIBIOS)/os/hal/lib/streams/chprintf.c \
$(CONSOLESRC) \
$(DEV_SRC) \
$(HW_LAYER_EMS) \
@ -177,9 +174,8 @@ CSRC = $(STARTUPSRC) \
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(CHCPPSRC) \
CPPSRC = $(ALLCPPSRC) \
$(DEV_SRC_CPP) \
$(BOARDSRC_CPP) \
$(HW_LAYER_EMS_CPP) \
$(HW_SENSORS_SRC) \
$(TUNERSTUDIO_SRC_CPP) \
@ -224,17 +220,8 @@ ifeq ($(CONFIGPATH),)
endif
INCDIR = .. $(CHIBIOS)/os/license \
$(PORTINC) \
$(OSALINC) \
$(KERNINC) \
$(TESTINC) \
$(STARTUPINC) \
$(HALINC) \
$(PLATFORMINC) \
$(BOARDINC) \
$(CHCPPINC) \
$(CHIBIOS)/os/hal/lib/streams \
INCDIR = $(ALLINC) \
.. \
$(CHIBIOS)/os/various \
$(CHIBIOS)/os/ex/ST \
$(CHIBIOS)/os/hal/lib/peripherals/sensors \
@ -281,8 +268,12 @@ BUILDDIR=blbuild
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
ifeq ($(CROSS_COMPILE),)
#TRGT = arm-elf-
TRGT = arm-none-eabi-
else
TRGT = $(CROSS_COMPILE)
endif
CC = $(CCPREFIX) $(TRGT)gcc
CPPC = $(CCPREFIX) $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.

3
firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk
View File

@ -15,7 +15,8 @@ STARTUPINC = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/devices/S6E2CxAH \
$(CHIBIOS)/os/common/ext/CMSIS/include \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
STARTUPLD = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CYPRESS = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)

268
firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h
View File

@ -193,21 +193,6 @@ typedef enum {
ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
} adcerror_t;
/**
* @brief Type of a structure representing an ADC driver.
*/
typedef struct ADCDriver ADCDriver;
/**
* @brief ADC notification callback type.
*
* @param[in] adcp pointer to the @p ADCDriver object triggering the
* callback
* @param[in] buffer pointer to the most recent samples data
* @param[in] n number of buffer rows available starting from @p buffer
*/
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
/**
* @brief ADC error callback type.
*
@ -217,193 +202,86 @@ typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
*/
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
/**
* @brief Conversion group configuration structure.
* @details This implementation-dependent structure describes a conversion
* operation.
*/
typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
adc_channels_num_t num_channels;
/**
* @brief Callback function associated to the group or @p NULL.
*/
adccallback_t end_cb;
/**
* @brief Error callback or @p NULL.
*/
adcerrorcallback_t error_cb;
/* End of the mandatory fields.*/
/* [andreika]: these are STM32-compatible fields, we'll convert them into Cypress ones */
/**
* @brief ADC CR1 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR1_SCAN that is enforced inside the driver.
*/
uint32_t cr1;
/**
* @brief ADC CR2 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
* enforced inside the driver.
*/
uint32_t cr2;
/**
* @brief ADC SMPR1 register initialization data.
* @details In this field must be specified the sample times for channels
* 10...18.
*/
uint32_t smpr1;
/**
* @brief ADC SMPR2 register initialization data.
* @details In this field must be specified the sample times for channels
* 0...9.
*/
uint32_t smpr2;
/**
* @brief ADC watchdog high threshold register.
* @details This field defines the high threshold of the analog watchdog.
*/
uint16_t htr;
/**
* @brief ADC watchdog low threshold register.
* @details This field defines the low threshold of the analog watchdog.
*/
uint16_t ltr;
/**
* @brief ADC SQR1 register initialization data.
* @details Conversion group sequence 13...16 + sequence length.
*/
uint32_t sqr1;
/**
* @brief ADC SQR2 register initialization data.
* @details Conversion group sequence 7...12.
*/
uint32_t sqr2;
/**
* @brief ADC SQR3 register initialization data.
* @details Conversion group sequence 1...6.
*/
uint32_t sqr3;
/* [andreika]: these are NOT STM32-compatible fields! But STM32 has only 16 ADC channels, and we need almost 32! */
/**
* @brief ADC SQR4 register initialization data.
* @details Conversion group sequence 18...23.
*/
uint32_t sqr4;
/**
* @brief ADC SQR5 register initialization data.
* @details Conversion group sequence 24...29.
*/
uint32_t sqr5;
} ADCConversionGroup;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
* @brief Low level fields of the ADC configuration structure.
*/
typedef struct {
/* Perform first time calibration */
bool calibrate;
} ADCConfig;
#define adc_lld_configuration_group_fields \
/* [dron_gus]: is there any reason to keep comatibility with stm32 drivers? */ \
/* [andreika]: these are STM32-compatible fields, we'll convert them into Cypress ones */ \
/* ADC CR1 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR1_SCAN that is enforced inside the driver.*/ \
uint32_t cr1; \
/* ADC CR2 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
enforced inside the driver.*/ \
uint32_t cr2; \
/* ADC SMPR1 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
10...18.*/ \
uint32_t smpr1; \
/* ADC SMPR2 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
0...9.*/ \
uint32_t smpr2; \
/* ADC watchdog high threshold register. \
NOTE: This field defines the high threshold of the analog watchdog.*/ \
uint16_t htr; \
/* ADC watchdog low threshold register. \
NOTE: This field defines the low threshold of the analog watchdog.*/ \
uint16_t ltr; \
/* ADC SQR1 register initialization data. \
NOTE: Conversion group sequence 13...16 + sequence length.*/ \
uint32_t sqr1; \
/* ADC SQR2 register initialization data. */ \
uint32_t sqr2; \
/* ADC SQR3 register initialization data. */ \
uint32_t sqr3; \
/* ADC SQR4 register initialization data. */ \
uint32_t sqr4; \
/* ADC SQR5 register initialization data. */ \
uint32_t sqr5
/**
* @brief Structure representing an ADC driver.
* @brief Low level fields of the ADC configuration structure.
*/
struct ADCDriver {
/**
* @brief Driver state.
*/
adcstate_t state;
/**
* @brief Current configuration data.
*/
const ADCConfig *config;
/**
* @brief Current samples buffer pointer or @p NULL.
*/
adcsample_t *samples;
/**
* @brief Current samples buffer depth or @p 0.
*/
size_t depth;
/**
* @brief Current conversion group pointer or @p NULL.
*/
const ADCConversionGroup *grpp;
#if ADC_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
mutex_t mutex;
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the PDL driver structure.
*/
stc_adcn_t *adc;
#define adc_lld_config_fields \
/* Perform first time calibration */ \
bool calibrate; \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/**
* @brief Pointer to the PDL driver config structures.
*/
stc_adc_config_t stcAdcConfig;
stc_adc_scan_t stcScanCfg;
/**
* @brief Pointer to IRQ callback structures.
*/
stc_adc_irq_en_t stcIrqEn;
stc_adc_irq_cb_t stcIrqCb;
/**
* @brief Number of samples expected.
*/
size_t number_of_samples;
/**
* @brief Current position in the buffer.
*/
volatile size_t current_index;
/**
* @brief Channel group index used to select software or hardware conversion triggering.
*/
uint32_t channelGroup;
/**
* @brief Bitmask of channels for ADC conversion.
*/
int8_t channelHwIndices[ADC_NUM_CHANNELS];
/**
* @brief Reciprocal to channelHwIndices.
*/
int8_t channelLogicIndices[ADC_NUM_CHANNELS];
bool wasInit;
/* We don't want to init ADC driver every time, so we check if settings are changed */
int8_t oldChannelHwIndices[ADC_NUM_CHANNELS];
adc_channels_num_t oldNumChannels;
size_t oldDepth;
/* The size of ADC FIFO buffer */
int fifoSize;
};
/**
* @brief Low level fields of the ADC driver structure.
*/
#define adc_lld_driver_fields \
/* Pointer to the PDL driver structure. */ \
stc_adcn_t *adc; \
/* Pointer to the PDL driver config structures. */ \
stc_adc_config_t stcAdcConfig; \
stc_adc_scan_t stcScanCfg; \
/* Pointer to IRQ callback structures. */ \
stc_adc_irq_en_t stcIrqEn; \
stc_adc_irq_cb_t stcIrqCb; \
/* Number of samples expected. */ \
size_t number_of_samples; \
/* Current position in the buffer. */ \
volatile size_t current_index; \
/* Channel group index used to select software or hardware conversion triggering. */ \
uint32_t channelGroup; \
/* Bitmask of channels for ADC conversion. */ \
int8_t channelHwIndices[ADC_NUM_CHANNELS]; \
/* Reciprocal to channelHwIndices. */ \
int8_t channelLogicIndices[ADC_NUM_CHANNELS]; \
bool wasInit; \
/* We don't want to init ADC driver every time, so we check if settings are changed */ \
int8_t oldChannelHwIndices[ADC_NUM_CHANNELS]; \
adc_channels_num_t oldNumChannels; \
size_t oldDepth; \
/* The size of ADC FIFO buffer */ \
int fifoSize
/*===========================================================================*/
/* Driver macros. */

13
firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.c
View File

@ -403,6 +403,19 @@ void can_lld_receive(CANDriver *canp,
// todo:
}
/**
* @brief Tries to abort an ongoing transmission.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] mailbox mailbox number
*
* @notapi
*/
void can_lld_abort(CANDriver *canp,
canmbx_t mailbox) {
/* tries, but fails.... someone, please implement this. */
}
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
/**
* @brief Enters the sleep mode.

2
firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.h
View File

@ -353,6 +353,8 @@ extern "C" {
void can_lld_receive(CANDriver *canp,
canmbx_t mailbox,
CANRxFrame *ctfp);
void can_lld_abort(CANDriver *canp,
canmbx_t mailbox);
#if CAN_USE_SLEEP_MODE
void can_lld_sleep(CANDriver *canp);
void can_lld_wakeup(CANDriver *canp);

6
firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c
View File

@ -57,6 +57,7 @@ SPIDriver SPID2;
/* Driver local functions. */
/*===========================================================================*/
static en_cs_pin_sel_t spi_detectPCS(bool isMaster, ioportid_t ssport, uint16_t sspad, int *alt) {
(void)isMaster;
*alt = PAL_MODE_ALTERNATIVE_SPI;
// todo: check if PCS corresponds to SPI number
if (ssport == GPIOG && sspad == 11) // P7B
@ -91,6 +92,7 @@ static int32_t spi_detectBaudRate(SPIDriver *spip) {
/*===========================================================================*/
static void spi_lld_master_tx_callback(SPIDriver *spip) {
(void)spip;
//!!!!!!!!!!!!!
#if 0
if (spip->csioSendCnt >= spip->csioTxBufSize) {
@ -106,6 +108,7 @@ static void spi_lld_master_tx_callback(SPIDriver *spip) {
}
static void spi_lld_master_rx_callback(SPIDriver *spip) {
(void)spip;
//!!!!!!!!!!!!!
#if 0
if (spip->csioRxBuf != NULL) {
@ -311,6 +314,8 @@ void spi_lld_unselect(SPIDriver *spip) {
* @notapi
*/
void spi_lld_ignore(SPIDriver *spip, size_t n) {
(void)spip;
(void)n;
// todo: implement
/*
spip->count = n;
@ -407,6 +412,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
* @notapi
*/
void spi_lld_abort(SPIDriver *spip) {
(void)spip;
// todo: implement
#if 0
//SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

125
firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h
View File

@ -88,11 +88,6 @@
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a structure representing an SPI driver.
*/
typedef struct SPIDriver SPIDriver;
/**
* @brief SPI notification callback type.
*
@ -102,100 +97,40 @@ typedef struct SPIDriver SPIDriver;
typedef void (*spicallback_t)(SPIDriver *spip);
/**
* @brief Driver configuration structure.
* @brief Low level fields of the SPI configuration structure.
*/
typedef struct {
#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__)
/**
* @brief Enables the circular buffer mode.
*/
bool circular;
#endif
/**
* @brief Operation complete callback or @p NULL.
*/
spicallback_t end_cb;
/* End of the mandatory fields.*/
/**
* @brief The chip select line port - when not using pcs.
*/
ioportid_t ssport;
/**
* @brief The chip select line pad number - when not using pcs.
*/
uint16_t sspad;
/**
* @brief SPI CR1 register initialization data.
*/
uint16_t cr1;
/**
* @brief SPI CR2 register initialization data.
*/
uint16_t cr2;
} SPIConfig;
#define spi_lld_config_fields \
/* The chip select port. */ \
ioportid_t ssport; \
/* The chip select pad number. */ \
uint_fast8_t sspad; \
/* SPI CR1 register initialization data.*/ \
uint16_t cr1; \
/* SPI CR2 register initialization data.*/ \
/* Actually noy used, keep for compatibility with stm32 */ \
uint16_t cr2
/**
* @brief Structure representing a SPI driver.
* @brief Low level fields of the SPI driver structure.
*/
struct SPIDriver {
/**
* @brief Driver state.
*/
spistate_t state;
/**
* @brief Current configuration data.
*/
const SPIConfig *config;
#if SPI_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
mutex_t mutex;
#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the SPIx registers block.
*/
volatile stc_mfsn_csio_t *spi;
/**
* PDL internal structures.
*/
stc_mfs_csio_config_t stcMfsCsioCfg;
stc_csio_cs_t stcCsioCsConfig;
stc_csio_irq_cb_t stcCsioIrqCb;
en_cs_pin_sel_t stcCsioCsPin;
/**
* @brief Master or Slave.
*/
bool isMaster;
/**
* @brief Transfer flags (including kLPSPI_MasterPcs*) for this SPI config.
*/
int32_t flags;
/**
* @brief Transfer buffers.
*/
uint8_t *csioTxBuf;
uint8_t *csioRxBuf;
uint32_t csioTxBufSize, csioRxBufSize;
uint32_t csioReceiveCnt, csioSendCnt;
volatile uint16_t u16RxBufFillCnt;
};
#define spi_lld_driver_fields \
/* Pointer to the SPIx registers block. */ \
volatile stc_mfsn_csio_t *spi; \
/* PDL internal structures. */ \
stc_mfs_csio_config_t stcMfsCsioCfg; \
stc_csio_cs_t stcCsioCsConfig; \
stc_csio_irq_cb_t stcCsioIrqCb; \
en_cs_pin_sel_t stcCsioCsPin; \
/* Master or Slave. */ \
bool isMaster; \
/* Transfer flags (including kLPSPI_MasterPcs*) for this SPI config. */ \
int32_t flags; \
/* Transfer buffers. */ \
uint8_t *csioTxBuf; \
uint8_t *csioRxBuf; \
uint32_t csioTxBufSize, csioRxBufSize; \
uint32_t csioReceiveCnt, csioSendCnt; \
volatile uint16_t u16RxBufFillCnt
/*===========================================================================*/
/* Driver macros. */

2
firmware/config/boards/hellen/cypress/board.mk
View File

@ -20,7 +20,7 @@ BOARDINC += $(PDL_DIR)/driver $(PDL_DIR)/driver/gpio $(PDL_DIR)/driver/usb $(PDL
BOARDCPPSRC += $(CONTROLLERS_ALGO_AUTO_GENERATED_ENUMS)
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/cypress_S6E2CxAH.ld
LDSCRIPT= $(STARTUPLD_CYPRESS)/cypress_S6E2CxAH.ld
#PLATFORMSRC += $(PLATFORMSRC_CONTRIB)
#PLATFORMINC += $(PLATFORMINC_CONTRIB)

46
firmware/config/boards/hellen/cypress/chconf.h
View File

@ -32,7 +32,7 @@
#define STM32_SYSCLK 192000000 // 192 MHz
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_5_1_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*
* __process_stack_size__ and __process_stack_size__ defaults are each hard-coded as 0x400 in ChibiOS rules.mk files
@ -425,6 +425,50 @@
#define CH_CFG_USE_OBJ_FIFOS FALSE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES FALSE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/

3
firmware/config/boards/hellen/cypress/halconf.h
View File

@ -28,6 +28,9 @@
#ifndef _HALCONF_H_
#define _HALCONF_H_
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**

3
firmware/config/boards/kinetis/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_ke1xf.mk
View File

@ -16,7 +16,8 @@ STARTUPINC = $(KINETIS_CONTRIB)/os/common/startup/ARMCMx/devices/KE1xF \
$(CHIBIOS)/os/common/ext/CMSIS/include \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
STARTUPLD = $(KINETIS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_KINETIS = $(KINETIS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)

231
firmware/config/boards/kinetis/OS/os/hal/ports/KINETIS/LLD/ADCv2/hal_adc_lld.h
View File

@ -204,21 +204,6 @@ typedef enum {
ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
} adcerror_t;
/**
* @brief Type of a structure representing an ADC driver.
*/
typedef struct ADCDriver ADCDriver;
/**
* @brief ADC notification callback type.
*
* @param[in] adcp pointer to the @p ADCDriver object triggering the
* callback
* @param[in] buffer pointer to the most recent samples data
* @param[in] n number of buffer rows available starting from @p buffer
*/
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
/**
* @brief ADC error callback type.
*
@ -228,82 +213,46 @@ typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
*/
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
/**
* @brief Conversion group configuration structure.
* @details This implementation-dependent structure describes a conversion
* operation.
* @brief Low level fields of the ADC configuration structure.
*/
typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
adc_channels_num_t num_channels;
/**
* @brief Callback function associated to the group or @p NULL.
*/
adccallback_t end_cb;
/**
* @brief Error callback or @p NULL.
*/
adcerrorcallback_t error_cb;
/* End of the mandatory fields.*/
#ifdef KE1xF
/* [andreika]: these are STM32-compatible fields, we'll convert them into Kinetis ones */
/**
* @brief ADC CR1 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR1_SCAN that is enforced inside the driver.
*/
uint32_t cr1;
/**
* @brief ADC CR2 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
* enforced inside the driver.
*/
uint32_t cr2;
/**
* @brief ADC SMPR1 register initialization data.
* @details In this field must be specified the sample times for channels
* 10...18.
*/
uint32_t smpr1;
/**
* @brief ADC SMPR2 register initialization data.
* @details In this field must be specified the sample times for channels
* 0...9.
*/
uint32_t smpr2;
/**
* @brief ADC watchdog high threshold register.
* @details This field defines the high threshold of the analog watchdog.
*/
uint16_t htr;
/**
* @brief ADC watchdog low threshold register.
* @details This field defines the low threshold of the analog watchdog.
*/
uint16_t ltr;
/**
* @brief ADC SQR1 register initialization data.
* @details Conversion group sequence 13...16 + sequence length.
*/
uint32_t sqr1;
/**
* @brief ADC SQR2 register initialization data.
* @details Conversion group sequence 7...12.
*/
uint32_t sqr2;
/**
* @brief ADC SQR3 register initialization data.
* @details Conversion group sequence 1...6.
*/
uint32_t sqr3;
#else
#define adc_lld_configuration_group_fields \
/* [andreika]: these are STM32-compatible fields, we'll convert them into Kinetis ones */ \
/* ADC CR1 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR1_SCAN that is enforced inside the driver.*/ \
uint32_t cr1; \
/* ADC CR2 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
enforced inside the driver.*/ \
uint32_t cr2; \
/* ADC SMPR1 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
10...18.*/ \
uint32_t smpr1; \
/* ADC SMPR2 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
0...9.*/ \
uint32_t smpr2; \
/* ADC watchdog high threshold register. \
NOTE: This field defines the high threshold of the analog watchdog.*/ \
uint16_t htr; \
/* ADC watchdog low threshold register. \
NOTE: This field defines the low threshold of the analog watchdog.*/ \
uint16_t ltr; \
/* ADC SQR1 register initialization data. \
NOTE: Conversion group sequence 13...16 + sequence length.*/ \
uint32_t sqr1; \
/* ADC SQR2 register initialization data. \
NOTE: Conversion group sequence 7...12.*/ \
uint32_t sqr2; \
/* ADC SQR3 register initialization data. \
NOTE: Conversion group sequence 1...6.*/ \
uint32_t sqr3
#if 0
/**
* @brief Bitmask of channels for ADC conversion.
*/
@ -319,94 +268,34 @@ typedef struct {
*/
uint32_t sc3;
#endif
} ADCConversionGroup;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
* @brief Low level fields of the ADC configuration structure.
*/
typedef struct {
/* Perform first time calibration */
bool calibrate;
} ADCConfig;
#define adc_lld_config_fields \
/* Perform first time calibration */ \
bool calibrate
/**
* @brief Structure representing an ADC driver.
* @brief Low level fields of the ADC driver structure.
*/
struct ADCDriver {
/**
* @brief Driver state.
*/
adcstate_t state;
/**
* @brief Current configuration data.
*/
const ADCConfig *config;
/**
* @brief Current samples buffer pointer or @p NULL.
*/
adcsample_t *samples;
/**
* @brief Current samples buffer depth or @p 0.
*/
size_t depth;
/**
* @brief Current conversion group pointer or @p NULL.
*/
const ADCConversionGroup *grpp;
#if ADC_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
mutex_t mutex;
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the ADCx registers block.
*/
ADC_TypeDef *adc;
/**
* @brief Number of samples expected.
*/
size_t number_of_samples;
/**
* @brief Current position in the buffer.
*/
size_t current_index;
/**
* @brief Current channel index into group channel_mask.
*/
size_t current_channel;
#ifdef KE1xF
/**
* @brief ADC12 driver config.
*/
adc12_config_t adc12Cfg;
/**
* @brief Current channel config struct.
*/
adc12_channel_config_t adc12ChannelCfg;
/**
* @brief Channel group index used to select software or hardware conversion triggering.
*/
uint32_t channelGroup;
/**
* @brief Bitmask of channels for ADC conversion.
*/
int8_t channelIndices[ADC_NUM_CHANNELS];
#endif /* KE1xF */
};
#define adc_lld_driver_fields \
/* Pointer to the ADCx registers block. */ \
ADC_TypeDef *adc; \
/* Number of samples expected. */ \
size_t number_of_samples; \
/* Current position in the buffer. */ \
size_t current_index; \
/* Current channel index into group channel_mask. */ \
size_t current_channel; \
/* ADC12 driver config. */ \
adc12_config_t adc12Cfg; \
/* Current channel config struct. */ \
adc12_channel_config_t adc12ChannelCfg; \
/* Channel group index used to select software or hardware conversion triggering. */ \
uint32_t channelGroup; \
/* Bitmask of channels for ADC conversion. */ \
int8_t channelIndices[ADC_NUM_CHANNELS]
/*===========================================================================*/
/* Driver macros. */

115
firmware/config/boards/kinetis/OS/os/hal/ports/KINETIS/LLD/SPIv2/hal_spi_lld.h
View File

@ -114,11 +114,6 @@
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a structure representing an SPI driver.
*/
typedef struct SPIDriver SPIDriver;
/**
* @brief SPI notification callback type.
*
@ -128,96 +123,34 @@ typedef struct SPIDriver SPIDriver;
typedef void (*spicallback_t)(SPIDriver *spip);
/**
* @brief Driver configuration structure.
* @brief Low level fields of the SPI configuration structure.
*/
typedef struct {
#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__)
/**
* @brief Enables the circular buffer mode.
*/
bool circular;
#endif
/**
* @brief Operation complete callback or @p NULL.
*/
spicallback_t end_cb;
/* End of the mandatory fields.*/
/**
* @brief The chip select line port - when not using pcs.
*/
ioportid_t ssport;
/**
* @brief The chip select line pad number - when not using pcs.
*/
uint16_t sspad;
/**
* @brief SPI CR1 register initialization data.
*/
uint16_t cr1;
/**
* @brief SPI CR2 register initialization data.
*/
uint16_t cr2;
} SPIConfig;
#define spi_lld_config_fields \
/* The chip select port. */ \
ioportid_t ssport; \
/* The chip select pad number. */ \
uint_fast8_t sspad; \
/* SPI CR1 register initialization data.*/ \
uint16_t cr1; \
/* SPI CR2 register initialization data.*/ \
uint16_t cr2
/**
* @brief Structure representing a SPI driver.
* @brief Low level fields of the SPI driver structure.
*/
struct SPIDriver {
/**
* @brief Driver state.
*/
spistate_t state;
/**
* @brief Current configuration data.
*/
const SPIConfig *config;
#if SPI_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
mutex_t mutex;
#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
SPI_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the SPIx registers block.
*/
LPSPI_Type *spi;
/**
* @brief Master or Slave.
*/
bool isMaster;
/**
* @brief Stores the data for SPI master transfer.
*/
lpspi_transfer_t handleXfer;
/**
* @brief Transfer flags (including kLPSPI_MasterPcs*) for this SPI config.
*/
int32_t flags;
/**
* @brief IRQ callback handle for SPI master non-blocking transfer.
*/
lpspi_master_handle_t masterHandle;
/**
* @brief IRQ callback handle for SPI slave non-blocking transfer.
*/
lpspi_slave_handle_t slaveHandle;
};
#define spi_lld_driver_fields \
/* Pointer to the SPIx registers block. */ \
LPSPI_Type *spi; \
/* Master or Slave. */ \
bool isMaster; \
/* Stores the data for SPI master transfer. */ \
lpspi_transfer_t handleXfer; \
/* Transfer flags (including kLPSPI_MasterPcs*) for this SPI config. */ \
int32_t flags; \
/* IRQ callback handle for SPI master non-blocking transfer. */ \
lpspi_master_handle_t masterHandle; \
/* IRQ callback handle for SPI slave non-blocking transfer. */ \
lpspi_slave_handle_t slaveHandle
/*===========================================================================*/
/* Driver macros. */

10
firmware/config/boards/kinetis/OS/os/hal/ports/KINETIS/LLD/UARTv2/hal_uart_lld.h
View File

@ -147,6 +147,10 @@ typedef struct {
* @brief Receive error callback.
*/
uartecb_t rxerr_cb;
/**
* @brief Receiver timeout (idle) callback.
*/
uartcb_t timeout_cb;
/* End of the mandatory fields.*/
/**
* @brief Bit rate.
@ -164,12 +168,6 @@ typedef struct {
* @brief Initialization value for the CR3 register.
*/
uint16_t cr3;
/* Additional (optional) handlers. Placed here for the struct compatibility.*/
/**
* @brief Receiver timeout (idle) callback.
* @details Handles an idle interrupt for USARTv1.
*/
uartcb_t timeout_cb;
/**
* @brief Half-transfer receive buffer callback.
*/

2
firmware/config/boards/kinetis/board.mk
View File

@ -12,7 +12,7 @@ BOARDINC += $(BOARD_DIR)/config/controllers/algo
BOARDCPPSRC += $(CONTROLLERS_ALGO_AUTO_GENERATED_ENUMS)
# Define linker script file here
LDSCRIPT = $(STARTUPLD)/MKE1xF512.ld
LDSCRIPT = $(STARTUPLD_KINETIS)/MKE1xF512.ld
CONFDIR = $(BOARD_DIR)

46
firmware/config/boards/kinetis/chconf.h
View File

@ -32,7 +32,7 @@
#define STM32_SYSCLK 168000000
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_5_1_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*
* __process_stack_size__ and __process_stack_size__ defaults are each hard-coded as 0x400 in ChibiOS rules.mk files
@ -424,6 +424,50 @@
#define CH_CFG_USE_OBJ_FIFOS FALSE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES FALSE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/

3
firmware/config/boards/kinetis/halconf.h
View File

@ -28,6 +28,9 @@
#ifndef _HALCONF_H_
#define _HALCONF_H_
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**

31
firmware/config/boards/nucleo_f746/STM32F746xG.ld
View File

@ -25,22 +25,22 @@
*/
MEMORY
{
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
/* let's hide since it overlaps with ram0 ram1 : org = 0x20010000, len = 240k*/ /* SRAM1 */
/* let's hide since it overlaps with ram0 ram2 : org = 0x2004C000, len = 16k*/ /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
@ -130,3 +130,6 @@ INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Memory rules inclusion.*/
INCLUDE rules_memory.ld

37
firmware/config/boards/nucleo_f767/STM32F76xxI.ld
View File

@ -26,23 +26,23 @@
*/
MEMORY
{
bl : org = 0x08000000, len = 16k /* bootloader section */
flash0 : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 1992k : 2048k
flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */ /* TODO: do we need BOOTLOADER logic here? */
flash2 : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0
ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
bl : org = 0x08000000, len = 16k /* bootloader section */
flash0 (rx) : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 1992k : 2048k
flash1 (rx) : org = 0x00200000, len = 2M /* Flash as ITCM */ /* TODO: do we need BOOTLOADER logic here? */
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
@ -132,3 +132,6 @@ INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Memory rules inclusion.*/
INCLUDE rules_memory.ld

54
firmware/config/chconf_common.h
View File

@ -47,30 +47,12 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
/*===========================================================================*/
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
* @name Kernel hooks
* @{
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
contextSwitchHook(); \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
irqEnterHook(); \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
irqExitHook(); \
}
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
@ -89,6 +71,32 @@ extern "C" {
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { threadInitHook(tp); }
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
threadInitHook(tp); \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
contextSwitchHook(); \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
irqEnterHook(); \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
irqExitHook(); \
}
#endif /* CONFIG_CHCONF_COMMON_H_ */

135
firmware/config/stm32f4ems/chconf.h
View File

@ -29,7 +29,7 @@
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_5_1_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*
* __process_stack_size__ and __process_stack_size__ defaults are each hard-coded as 0x400 in ChibiOS rules.mk files
@ -65,16 +65,20 @@
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 1000
#endif
/**
* @brief Time intervals data size.
@ -134,21 +138,6 @@
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
@ -337,6 +326,28 @@
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
@ -345,7 +356,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES FALSE
#endif
/**
* @brief I/O Queues APIs.
@ -366,6 +379,21 @@
#define CH_CFG_USE_MEMCORE FALSE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
@ -392,20 +420,7 @@
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC FALSE
#endif
/**
* @brief Objects FIFOs APIs.
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
@ -415,6 +430,50 @@
#define CH_CFG_USE_OBJ_FIFOS FALSE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES FALSE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/
@ -479,6 +538,13 @@
#define CH_CFG_FACTORY_OBJ_FIFOS FALSE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES FALSE
#endif
/** @} */
/*===========================================================================*/
@ -629,10 +695,6 @@
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
@ -645,6 +707,7 @@
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
@ -654,6 +717,7 @@
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
@ -692,7 +756,6 @@
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/

16
firmware/config/stm32f4ems/halconf.h
View File

@ -25,18 +25,14 @@
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/* THIS IS HACK: to allow smooth transition to ChibiOS with ELF support we
* need to disable hal_flash.h until we move to ChibiOS EFL driver.
* hal_flash.h in ChibiOS has definitions that conflict with current RusEFI
* flash driver.
* but it is included unconditionaly from hal.h */
#define HAL_FLASH_H
/**
* @brief Enables the FLASH subsystem.
*/
@ -411,6 +407,6 @@
#include "halconf_community.h"
#endif /* _HALCONF_H_ */
#endif /* HALCONF_H */
/** @} */

34
firmware/config/stm32f4ems/mcuconf.h
View File

@ -59,6 +59,10 @@
*/
#define STM32F4xx_MCUCONF
#define STM32F405_MCUCONF
#define STM32F415_MCUCONF
#define STM32F407_MCUCONF
#define STM32F417_MCUCONF
/*
* HAL driver system settings.
@ -156,21 +160,21 @@
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXT_IRQ_PRIORITY ICU_PRIORITY
#define STM32_EXT_EXTI0_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI1_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI2_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI3_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI4_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI16_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI19_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI20_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
#define STM32_IRQ_EXTI_PRIORITY ICU_PRIORITY
#define STM32_IRQ_EXTI0_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI1_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI2_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI3_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI4_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI5_9_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI10_15_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI16_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI17_PRIORITY 15 /* why? */
#define STM32_IRQ_EXTI18_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI19_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI20_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI21_PRIORITY 15 /* why? */
#define STM32_IRQ_EXTI22_PRIORITY 15 /* why? */
/*
* GPT driver system settings.

135
firmware/config/stm32f7ems/chconf.h
View File

@ -29,7 +29,7 @@
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_5_1_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*
* __process_stack_size__ and __process_stack_size__ defaults are each hard-coded as 0x400 in ChibiOS rules.mk files
@ -65,16 +65,20 @@
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 1000
#endif
/**
* @brief Time intervals data size.
@ -134,21 +138,6 @@
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
@ -337,6 +326,28 @@
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
@ -345,7 +356,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES FALSE
#endif
/**
* @brief I/O Queues APIs.
@ -366,6 +379,21 @@
#define CH_CFG_USE_MEMCORE FALSE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
@ -392,20 +420,7 @@
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC FALSE
#endif
/**
* @brief Objects FIFOs APIs.
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
@ -415,6 +430,50 @@
#define CH_CFG_USE_OBJ_FIFOS FALSE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES FALSE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/** @} */
/*===========================================================================*/
@ -479,6 +538,13 @@
#define CH_CFG_FACTORY_OBJ_FIFOS FALSE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES FALSE
#endif
/** @} */
/*===========================================================================*/
@ -629,10 +695,6 @@
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
@ -645,6 +707,7 @@
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
@ -654,6 +717,7 @@
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
@ -692,7 +756,6 @@
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/

10
firmware/config/stm32f7ems/halconf.h
View File

@ -28,14 +28,10 @@
#ifndef HALCONF_H
#define HALCONF_H
#include "mcuconf.h"
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
/* THIS IS HACK: to allow smooth transition to ChibiOS with ELF support we
* need to disable hal_flash.h until we move to ChibiOS EFL driver.
* hal_flash.h in ChibiOS has definitions that conflict with current RusEFI
* flash driver.
* but it is included unconditionaly from hal.h */
#define HAL_FLASH_H
#include "mcuconf.h"
/**
* @brief Enables the FLASH subsystem.

97
firmware/config/stm32f7ems/mcuconf.h
View File

@ -17,6 +17,30 @@
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F7xx_MCUCONF
#define STM32F765_MCUCONF
#define STM32F767_MCUCONF
#define STM32F777_MCUCONF
#define STM32F769_MCUCONF
#define STM32F779_MCUCONF
/* for stm32f746_nucleo */
#define STM32F746_MCUCONF
#include "efifeatures.h"
/**
@ -177,21 +201,22 @@
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXT_IRQ_PRIORITY ICU_PRIORITY
#define STM32_EXT_EXTI0_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI1_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI2_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI3_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI4_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI16_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI19_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI20_IRQ_PRIORITY STM32_EXT_EXT_IRQ_PRIORITY
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
#define STM32_IRQ_EXTI_PRIORITY ICU_PRIORITY
#define STM32_IRQ_EXTI0_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI1_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI2_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI3_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI4_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI5_9_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI10_15_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI16_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI17_PRIORITY 15 /* why? */
#define STM32_IRQ_EXTI18_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI19_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI20_PRIORITY STM32_IRQ_EXTI_PRIORITY
#define STM32_IRQ_EXTI21_PRIORITY 15 /* why? */
#define STM32_IRQ_EXTI22_PRIORITY 15 /* why? */
#define STM32_IRQ_EXTI23_PRIORITY STM32_IRQ_EXTI_PRIORITY
/*
* GPT driver system settings.
@ -208,19 +233,21 @@
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
/*
* I2C driver system settings.
*/
@ -318,14 +345,14 @@
#define STM32_SERIAL_USE_USART6 TRUE
#define STM32_SERIAL_USE_UART7 FALSE
#define STM32_SERIAL_USE_UART8 FALSE
#define STM32_SERIAL_USART1_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_USART2_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_USART3_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_UART4_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_UART5_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_USART6_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_UART7_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_SERIAL_UART8_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_USART1_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_USART2_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_USART3_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_UART4_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_UART5_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_USART6_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_UART7_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
#define STM32_IRQ_UART8_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
/*
* SPI driver system settings.

14
firmware/console/binary/tunerstudio_io.cpp
View File

@ -42,9 +42,17 @@ extern SERIAL_USB_DRIVER TS_USB_DEVICE;
#elif TS_UART_MODE
/* Note: This structure is modified from the default ChibiOS layout! */
static UARTConfig tsUartConfig = {
.txend1_cb = NULL, .txend2_cb = NULL, .rxend_cb = NULL, .rxchar_cb = NULL, .rxerr_cb = NULL,
.speed = 0, .cr1 = 0, .cr2 = 0/*USART_CR2_STOP1_BITS*/ | USART_CR2_LINEN, .cr3 = 0,
.timeout_cb = NULL, .rxhalf_cb = NULL
.txend1_cb = NULL,
.txend2_cb = NULL,
.rxend_cb = NULL,
.rxchar_cb = NULL,
.rxerr_cb = NULL,
.timeout_cb = NULL,
.speed = 0,
.cr1 = 0,
.cr2 = 0/*USART_CR2_STOP1_BITS*/ | USART_CR2_LINEN,
.cr3 = 0,
.rxhalf_cb = NULL
};
#elif defined(TS_SERIAL_DEVICE)
static SerialConfig tsSerialConfig = { .speed = 0, .cr1 = 0, .cr2 = USART_CR2_STOP1_BITS | USART_CR2_LINEN, .cr3 = 0 };

14
firmware/console/connector_uart_dma.cpp
View File

@ -54,9 +54,17 @@ static void tsRxIRQIdleHandler(UARTDriver *uartp) {
/* Note: This structure is modified from the default ChibiOS layout! */
static UARTConfig tsDmaUartConfig = {
.txend1_cb = NULL, .txend2_cb = NULL, .rxend_cb = NULL, .rxchar_cb = NULL, .rxerr_cb = NULL,
.speed = 0, .cr1 = 0, .cr2 = 0/*USART_CR2_STOP1_BITS*/ | USART_CR2_LINEN, .cr3 = 0,
.timeout_cb = tsRxIRQIdleHandler, .rxhalf_cb = tsRxIRQHalfHandler
.txend1_cb = NULL,
.txend2_cb = NULL,
.rxend_cb = NULL,
.rxchar_cb = NULL,
.rxerr_cb = NULL,
.timeout_cb = tsRxIRQIdleHandler,
.speed = 0,
.cr1 = 0,
.cr2 = 0/*USART_CR2_STOP1_BITS*/ | USART_CR2_LINEN,
.cr3 = 0,
.rxhalf_cb = tsRxIRQHalfHandler
};
void startUartDmaConnector(UARTDriver *uartp DECLARE_CONFIG_PARAMETER_SUFFIX) {

2
firmware/console/console_io.cpp
View File

@ -172,11 +172,11 @@ UARTConfig uartConfig = {
.rxend_cb = NULL,
.rxchar_cb = NULL,
.rxerr_cb = NULL,
.timeout_cb = NULL,
.speed = 0,
.cr1 = 0,
.cr2 = 0/*USART_CR2_STOP1_BITS*/ | USART_CR2_LINEN,
.cr3 = 0,
.timeout_cb = NULL,
.rxhalf_cb = NULL
};

2
firmware/controllers/sensors/software_knock.cpp
View File

@ -22,7 +22,7 @@ static volatile size_t sampleCount = 0;
binary_semaphore_t knockSem;
static void completionCallback(ADCDriver* adcp, adcsample_t*, size_t) {
static void completionCallback(ADCDriver* adcp) {
palClearPad(GPIOD, 2);
if (adcp->state == ADC_COMPLETE) {

2
firmware/hw_layer/adc/adc_inputs.cpp
View File

@ -173,7 +173,7 @@ static ADCConversionGroup adcgrpcfgSlow = {
AdcDevice slowAdc(&adcgrpcfgSlow, slowAdcSampleBuf, ARRAY_SIZE(slowAdcSampleBuf));
void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n);
void adc_callback_fast(ADCDriver *adcp);
static ADCConversionGroup adcgrpcfgFast = {
.circular = FALSE,

1
firmware/hw_layer/digital_input/digital_input_icu.cpp
View File

@ -50,6 +50,7 @@ static ICUConfig wave_icucfg = {
.overflow_cb = NULL,
.channel = ICU_CHANNEL_1,
.dier = 0,
.arr = 0xFFFFFFFFU
};
static ArrayList<digital_input_s, 8> registeredIcus;

19
firmware/hw_layer/hardware.cpp
View File

@ -161,9 +161,12 @@ static int adcCallbackCounter = 0;
static volatile int averagedSamples[ADC_MAX_CHANNELS_COUNT];
static adcsample_t avgBuf[ADC_MAX_CHANNELS_COUNT];
void adc_callback_fast_internal(ADCDriver *adcp, adcsample_t *buffer, size_t n);
void adc_callback_fast_internal(ADCDriver *adcp);
void adc_callback_fast(ADCDriver *adcp) {
adcsample_t *buffer = adcp->samples;
//size_t n = adcp->depth;
void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
if (adcp->state == ADC_COMPLETE) {
fastAdc.invalidateSamplesCache();
@ -186,7 +189,7 @@ void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
}
// call the real callback (see below)
adc_callback_fast_internal(adcp, avgBuf, fastAdc.size());
adc_callback_fast_internal(adcp);
// reset the avg buffer & counter
for (int i = fastAdc.size() - 1; i >= 0; i--) {
@ -197,14 +200,18 @@ void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
}
}
#define adc_callback_fast adc_callback_fast_internal
#endif /* EFI_FASTER_UNIFORM_ADC */
/**
* This method is not in the adc* lower-level file because it is more business logic then hardware.
*/
void adc_callback_fast(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
#if EFI_FASTER_UNIFORM_ADC
void adc_callback_fast_internal(ADCDriver *adcp) {
#else
void adc_callback_fast(ADCDriver *adcp) {
#endif
adcsample_t *buffer = adcp->samples;
size_t n = adcp->depth;
(void) buffer;
(void) n;

38
simulator/Makefile
View File

@ -112,16 +112,19 @@ PROJECT_DIR = ../firmware
# Imported source files and paths
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/boards/simulator/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/SIMIA32/compilers/GCC/port.mk
# Other files (optional).
include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
#include $(CHIBIOS)/os/various/cpp_wrappers/chcpp.mk
ifeq ($(OS),Windows_NT)
include ${CHIBIOS}/os/hal/ports/simulator/win32/platform.mk
@ -142,25 +145,21 @@ include $(PROJECT_DIR)/util/util.mk
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = ${PORTSRC} \
${KERNSRC} \
${HALSRC} \
${PLATFORMSRC} \
CSRC = $(ALLCSRC) \
$(SYSTEMSRC) \
$(CONSOLESRC) \
$(CONTROLLERS_ALGO_SRC) \
$(CONTROLLERS_CORE_SRC) \
$(CONTROLLERS_SENSORS_SRC) \
$(ENGINES_SRC) \
$(BOARDSRC) \
$(CHIBIOS)/os/hal/lib/streams/memstreams.c \
$(CHIBIOS)/os/hal/lib/streams/chprintf.c \
$(UTILSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(UTILSRC_CPP) \
CPPSRC = $(ALLCPPSRC) \
$(CHIBIOS)/os/various/cpp_wrappers/ch.cpp \
$(UTILSRC_CPP) \
$(CONTROLLERS_ALGO_SRC_CPP) \
$(CONTROLLERS_SRC_CPP) \
$(PROJECT_DIR)/development/sensor_chart.cpp \
@ -187,26 +186,21 @@ CPPSRC = $(UTILSRC_CPP) \
ASMSRC = $(PORTASM)
INCDIR = . \
$(CHIBIOS)/os/license \
$(PORTINC) \
$(KERNINC) \
$(OSALINC) \
$(HALINC) \
$(CHCPPINC) \
$(PLATFORMINC) \
$(BOARDINC) \
$(ALLINC) \
$(CHIBIOS)/os/various/cpp_wrappers \
$(UTIL_INC) \
$(PROJECT_DIR)/init \
$(CONSOLE_INC) \
$(PROJECT_DIR)/config/engines \
$(PROJECT_DIR)/ext_algo \
$(HW_LAYER_DRIVERS_INC) \
$(HW_LAYER_INC) $(HW_SENSORS_INC) \
$(HW_LAYER_DRIVERS_INC) \
$(HW_LAYER_INC) \
$(HW_SENSORS_INC) \
$(PROJECT_DIR)/hw_layer/algo \
$(PROJECT_DIR)/hw_layer/drivers/can \
$(HW_SENSORS_INC) \
$(DEVELOPMENT_DIR) \
$(CONTROLLERS_INC) \
$(DEVELOPMENT_DIR) \
$(CONTROLLERS_INC) \
${CHIBIOS}/os/various \
$(CHIBIOS)/os/hal/lib/streams \
simulator

46
simulator/chconf.h
View File

@ -29,7 +29,7 @@
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_5_1_
#define _CHIBIOS_RT_CONF_VER_6_1_
#define CHPRINTF_USE_FLOAT TRUE
@ -372,6 +372,50 @@
#define CH_CFG_USE_OBJ_FIFOS FALSE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES FALSE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES FALSE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES FALSE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included

3
simulator/halconf.h
View File

@ -28,6 +28,9 @@
#ifndef _HALCONF_H_
#define _HALCONF_H_
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
/*#include "mcuconf.h"*/
/**