MRE legacy: comments about SPI flash

firmware/config/boards/microrusefi/board_storage.cpp

@@ -29,13 +29,16 @@
 #define EFI_FLASH_HOLD			Gpio::B11
 
 /* 8 Mbytes */
+/* Not used, just FYI */
 #define EFI_FLASH_SIZE (8 * 1024 * 1024)
 
 /* Some fields in following struct are used for DMA transfers, so do not cache */
 NO_CACHE SNORDriver snor1;
 
 /*
- * Maximum speed SPI configuration (??MHz, CPHA=0, CPOL=0, MSb first).
+ * Maximum speed SPI configuration (Clock = Fpclk / 2 =  21 MHz, CPHA=0, CPOL=0, MSb first).
+ * SPI2 is clocked from APB1, APB1 clock is 42MHz
+ * W25Qxx supports up to 133MHz in single SPI mode
  */
 static const SPIConfig W25SpiCfg = {
 	.circular = false,
@@ -62,11 +65,26 @@ static const SNORConfig W25FlashConfig = {
 const MFSConfig mfsd_nor_config = {
 	.flashp			= (BaseFlash *)&snor1,
 	.erased			= 0xFFFFFFFFU,
-	.bank_size		= 64 * 1024U,
+#if 1
+	/* it takes:
+	 * 147 mS to write 25K of settings whithout garbage collector (when there is free space in current bank)
+	 * 4750 mS to write settings with garbage collection (packing and moving to another bank, erasing old one)
+	 * GC happens rougly every ((512 / 25) - 1) ~= 19 write */
+	.bank_size		= 512 * 1024U,
 	.bank0_start	= 0U,
 	.bank0_sectors	= 128U,	/* 128 * 4 K = 0.5 Mb */
 	.bank1_start	= 128U,
 	.bank1_sectors	= 128U
+#else
+	/* it takes:
+	 * same 147 mS to write setting without GC
+	 * 1500 mS to write setting with GC, but GC happens every time we write settings */
+	.bank_size		= 64 * 1024U,
+	.bank0_start	= 0U,
+	.bank0_sectors	= 16U,	/* 16 * 4 K = 64 Kb */
+	.bank1_start	= 16U,
+	.bank1_sectors	= 16U
+#endif
 };
 
 void boardInitMfs()