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only:variable shadowing should be avoided #5676

This commit is contained in:
rusefillc 2023-11-01 12:07:00 -04:00
parent fd308425a8
commit 91ba507d4b
2 changed files with 27 additions and 30 deletions
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25
firmware/hw_layer/drivers/gpio/l9779.cpp
View File

@ -171,8 +171,8 @@ struct L9779 : public GpioChip {
int spi_err_parity; /* parity errors in rx data */
int spi_err_frame; /* rx messages with bit 15 set */
int spi_err; /* rx messages with incorrect ADDR or WR fields */
uint16_t tx;
uint16_t rx;
uint16_t recentTx;
uint16_t recentRx;
};
static L9779 chips[BOARD_L9779_COUNT];
@ -271,9 +271,9 @@ int L9779::spi_rw(uint16_t tx, uint16_t *rx_ptr)
/* Ownership release. */
spiReleaseBus(spi);
/* statisctic and debug */
this->tx = tx;
this->rx = rx;
/* statistics and debug */
recentTx = tx;
recentRx = rx;
this->spi_cnt++;
if (rx_ptr)
@ -282,9 +282,9 @@ int L9779::spi_rw(uint16_t tx, uint16_t *rx_ptr)
/* validate reply */
ret = spi_validate(rx);
/* save last accessed register */
last_addr = MSG_GET_ADDR(this->tx);
last_addr = MSG_GET_ADDR(recentTx);
if (last_addr == MSG_READ_ADDR)
last_subaddr = MSG_GET_SUBADDR(this->tx);
last_subaddr = MSG_GET_SUBADDR(recentTx);
else
last_subaddr = REG_INVALID;
@ -319,16 +319,16 @@ int L9779::spi_rw_array(const uint16_t *tx, uint16_t *rx, int n)
spiUnselect(spi);
/* statistic and debug */
this->tx = tx[i];
this->rx = rxdata;
recentTx = tx[i];
recentRx = rxdata;
this->spi_cnt++;
/* validate reply */
ret = spi_validate(rxdata);
/* save last accessed register */
last_addr = MSG_GET_ADDR(this->tx);
last_addr = MSG_GET_ADDR(recentTx);
if (last_addr == MSG_READ_ADDR)
last_subaddr = MSG_GET_SUBADDR(this->tx);
last_subaddr = MSG_GET_SUBADDR(recentTx);
else
last_subaddr = REG_INVALID;
@ -627,12 +627,11 @@ brain_pin_diag_e L9779::getDiag(size_t pin)
int L9779::chip_init_data(void)
{
int i;
int ret = 0;
o_oe_mask = 0;
for (i = 0; i < L9779_DIRECT_OUTPUTS; i++) {
for (int i = 0; i < L9779_DIRECT_OUTPUTS; i++) {
if (cfg->direct_gpio[i].port == NULL)
continue;

32
firmware/hw_layer/drivers/gpio/tle8888.cpp
View File

@ -261,8 +261,8 @@ struct Tle8888 : public GpioChip {
int init_cnt;
int init_req_cnt;
int spi_cnt;
uint16_t tx;
uint16_t rx;
uint16_t recentTx;
uint16_t recentRx;
};
static Tle8888 chips[BOARD_TLE8888_COUNT];
@ -368,8 +368,8 @@ int Tle8888::spi_rw(uint16_t tx, uint16_t *rx_ptr)
spiReleaseBus(spi);
/* statisctic and debug */
this->tx = tx;
this->rx = rx;
recentTx = tx;
recentRx = rx;
this->spi_cnt++;
if (rx_ptr)
@ -420,8 +420,8 @@ int Tle8888::spi_rw_array(const uint16_t *tx, uint16_t *rx, int n)
spiUnselect(spi);
/* statistic and debug */
this->tx = tx[i];
this->rx = rxdata;
recentTx = tx[i];
recentRx = rxdata;
this->spi_cnt++;
/* validate reply and save last accessed register */
@ -471,7 +471,7 @@ int Tle8888::update_output()
* (at least until we start supporting hi-Z state) */
o_data |= o_pp_mask;
uint16_t tx[] = {
uint16_t updateTx[] = {
/* bridge config */
CMD_BRICONFIG(0, briconfig0),
/* output enables */
@ -483,7 +483,7 @@ int Tle8888::update_output()
CMD_CMD0((mr_manual ? REG_CMD0_MRSE : 0x0) |
((o_data & BIT(TLE8888_OUTPUT_MR)) ? REG_CMD0_MRON : 0x0))
};
ret = spi_rw_array(tx, NULL, efi::size(tx));
ret = spi_rw_array(updateTx, NULL, efi::size(updateTx));
if (ret == 0) {
/* atomic */
@ -500,7 +500,7 @@ int Tle8888::update_output()
int Tle8888::update_status_and_diag()
{
int ret = 0;
const uint16_t tx[] = {
const uint16_t diagTx[] = {
CMD_OUTDIAG(0),
CMD_OUTDIAG(1),
CMD_OUTDIAG(2),
@ -514,9 +514,9 @@ int Tle8888::update_status_and_diag()
CMD_OPSTAT(1),
CMD_OPSTAT(1)
};
uint16_t rx[efi::size(tx)];
uint16_t rx[efi::size(diagTx)];
ret = spi_rw_array(tx, rx, efi::size(tx));
ret = spi_rw_array(diagTx, rx, efi::size(diagTx));
if (ret == 0) {
/* the address and content of the selected register is transmitted with the
@ -639,7 +639,7 @@ int Tle8888::chip_init()
/* statistic */
init_cnt++;
uint16_t tx[] = {
uint16_t initTx[] = {
/* unlock */
CMD_CHIP_UNLOCK,
/* set INCONFIG - aux input mapping */
@ -695,7 +695,7 @@ int Tle8888::chip_init()
CMD_OE_SET
};
ret = spi_rw_array(tx, NULL, efi::size(tx));
ret = spi_rw_array(initTx, NULL, efi::size(initTx));
if (ret == 0) {
/* enable pins */
@ -1055,8 +1055,6 @@ brain_pin_diag_e Tle8888::getDiag(size_t pin)
}
int Tle8888::chip_init_data() {
int i;
int ret = 0;
o_direct_mask = 0;
@ -1080,7 +1078,7 @@ int Tle8888::chip_init_data() {
palClearPort(cfg->inj_en.port, PAL_PORT_BIT(cfg->inj_en.pad));
}
for (i = 0; i < TLE8888_DIRECT_MISC; i++) {
for (int i = 0; i < TLE8888_DIRECT_MISC; i++) {
/* Set some invalid default OUT number...
* Keeping this register default (0) will map one of input signals
* to OUT5 and no control over SPI for this pin will be possible.
@ -1091,7 +1089,7 @@ int Tle8888::chip_init_data() {
InConfig[i] = 25 - 1 - 4;
}
for (i = 0; i < TLE8888_DIRECT_OUTPUTS; i++) {
for (int i = 0; i < TLE8888_DIRECT_OUTPUTS; i++) {
int out = -1;
uint32_t mask;