Tle8888 stage 1 (#1404)
* TLE8888: implement diagnostic * TLE8888: add support for PP mode on OUT21..24 * tle8888: use helpers to extract register value from 16bit reply
This commit is contained in:
dron0gus
GitHub
parent
39c5f40d17
commit
98bca0cb23
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@ -227,8 +227,9 @@ int gpiochips_init(void)
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* return -1 if driver does not implemet setPadMode ops
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* else return value from gpiochip driver.
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*/
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int gpiochips_setPadMode(brain_pin_e pin, int mode)
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/* this fuction uses iomode_t that is related to STM32 (or other MCU)
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* output modes. Use some common enums? */
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int gpiochips_setPadMode(brain_pin_e pin, iomode_t mode)
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{
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struct gpiochip *chip = gpiochip_find(pin);
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@ -26,7 +26,7 @@ extern "C"
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struct gpiochip_ops {
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/* pin argument is pin number within gpio chip, not a global number */
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int (*setPadMode)(void *data, unsigned int pin, int mode);
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int (*setPadMode)(void *data, unsigned int pin, iomode_t mode);
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int (*writePad)(void *data, unsigned int pin, int value);
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int (*readPad)(void *data, unsigned int pin);
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brain_pin_diag_e (*getDiag)(void *data, unsigned int pin);
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@ -49,7 +49,7 @@ int gpiochips_setPinNames(brain_pin_e pin, const char **names);
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/* gpio extenders subsystem init */
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int gpiochips_init(void);
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int gpiochips_setPadMode(brain_pin_e pin, int mode);
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int gpiochips_setPadMode(brain_pin_e pin, iomode_t mode);
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int gpiochips_writePad(brain_pin_e pin, int value);
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int gpiochips_readPad(brain_pin_e pin);
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brain_pin_diag_e gpiochips_getDiag(brain_pin_e pin);
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@ -96,22 +96,31 @@ typedef enum {
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#define FWDStat1 0x38
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/* Status registers */
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#define CMD_OPSTAT0 CMD_R(0x34)
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#define CMD_OPSTAT1 CMD_R(0x35)
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#define CMD_OPSTAT(n) CMD_R(0x34 + ((n) & 0x01))
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#define CMD_WWDSTAT CMD_R(WWDStat)
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#define CMD_FWDSTAT0 CMD_R(FWDStat0)
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#define CMD_FWDSTAT1 CMD_R(FWDStat1)
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#define CMD_TECSTAT CMD_R(0x39)
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#define CMD_WdDiag CMD_R(0x2e)
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/* Diagnostic */
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#define CMD_DIAG(n) CMD_R(0x20 + ((n) & 0x01))
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#define CMD_VRSDIAG(n) CMD_R(0x22 + ((n) & 0x01))
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#define CMD_COMDIAG CMD_R(0x24)
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#define CMD_OUTDIAG(n) CMD_R(0x25 + ((n) & 0x07))
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#define CMD_PPOVDIAG CMD_R(0x2a)
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#define CMD_BRIDIAG(n) CMD_R(0x2b + ((n) & 0x01))
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#define CMD_IGNDIAG CMD_R(0x2d)
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#define CMD_WDDIAG CMD_R(0x2e)
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#define CMD_OUTCONFIG(n, d) CMD_WR(0x40 + (n), d)
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#define CMD_BRICONFIG(n, d) CMD_WR(0x46 + ((n) & 0x01), d)
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//#define CMD_VRSCONFIG0(d) CMD_WR(0x49, d)
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#define CMD_VRSCONFIG1(d) CMD_WR(0x4a, d)
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#define CMD_INCONFIG(n, d) CMD_WR(0x53 + (n & 0x03), d)
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#define CMD_DDCONFIG(n, d) CMD_WR(0x57 + (n & 0x03), d)
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#define CMD_OECONFIG(n, d) CMD_WR(0x5b + (n & 0x03), d)
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#define CMD_CONT(n, d) CMD_WR(0x7b + (n & 0x03), d)
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#define CMD_INCONFIG(n, d) CMD_WR(0x53 + ((n) & 0x03), d)
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#define CMD_DDCONFIG(n, d) CMD_WR(0x57 + ((n) & 0x03), d)
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#define CMD_OECONFIG(n, d) CMD_WR(0x5b + ((n) & 0x03), d)
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#define CMD_CONT(n, d) CMD_WR(0x7b + ((n) & 0x03), d)
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const uint8_t watchDogResponses[16][4] = {
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/* Reverse order:
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@ -133,6 +142,7 @@ const uint8_t watchDogResponses[16][4] = {
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{0x4E, 0xBE, 0x41, 0xB1},
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{0x01, 0xF1, 0x0E, 0xFE}
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};
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/*==========================================================================*/
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/* Driver exported variables. */
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/*==========================================================================*/
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@ -199,11 +209,22 @@ struct tle8888_priv {
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uint32_t o_direct_mask;
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/* output enabled mask */
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uint32_t o_oe_mask;
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/* push-pull enabled mask (for OUT21..OUT24 only) */
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/* this is overhead to store 4 bits in uint32_t
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* but I don't want any magic shift math */
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uint32_t o_pp_mask;
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tle8888_drv_state drv_state;
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/* diagnostic registers */
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uint8_t OutDiag[5];
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uint8_t BriDiag[2];
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uint8_t IgnDiag;
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/* status registers */
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uint16_t OpStat[2];
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uint8_t OpStat[2];
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/* last diagnostick was read */
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systime_t ts_diag;
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};
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static struct tle8888_priv chips[BOARD_TLE8888_COUNT];
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@ -300,12 +321,39 @@ static int tle8888_spi_rw(struct tle8888_priv *chip, uint16_t tx, uint16_t *rx)
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static int tle8888_update_output(struct tle8888_priv *chip)
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{
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int i;
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int ret = 0;
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uint8_t briconfig0 = 0;
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/* TODO: lock? */
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uint32_t out_data = chip->o_state;
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/* calculate briconfig0 */
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uint32_t out_low = out_data & chip->o_pp_mask;
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for (i = 20; i < 24; i++) {
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if (out_low & BIT(i)) {
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/* low-side switch mode */
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} else {
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/* else enable high-side switch mode */
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briconfig0 |= BIT((i - 20) * 2);
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}
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}
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/* TODO: set freewheeling bits in briconfig0? */
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/* output for push-pull pins is allways enabled
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* (at least until we start supporting hi-Z state) */
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out_data |= chip->o_pp_mask;
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/* TODO: apply hi-Z mask when support will be added */
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/* set value only for non-direct driven pins */
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uint32_t out_data = chip->o_state & (~chip->o_direct_mask);
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/* look like here is some conflict in case of
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* direct-driven PP output */
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out_data &= (~chip->o_direct_mask);
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/* bridge config */
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ret = tle8888_spi_rw(chip, CMD_BRICONFIG(0, briconfig0), NULL);
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for (int i = 0; i < 4; i++) {
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uint8_t od;
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@ -324,10 +372,10 @@ static int tle8888_update_output(struct tle8888_priv *chip)
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}
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/**
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* @brief read TLE8888 OpStat1 registers data.
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* @details Sends read command, then send same command and read reply
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* @brief read TLE8888 OpStat1 and diagnostic registers data.
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* @details Chained read of several registers
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*/
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static int tle8888_update_status(struct tle8888_priv *chip)
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static int tle8888_update_status_and_diag(struct tle8888_priv *chip)
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{
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int ret = 0;
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uint16_t rx = 0;
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@ -338,19 +386,62 @@ static int tle8888_update_status(struct tle8888_priv *chip)
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/* the address and content of the selected register is transmitted with the
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* next SPI transmission (for not existing addresses or wrong access mode
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* the data is always '0' */
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/* this is quite expensive to call tle8888_spi_rw on each register read
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* TODO: implement tle8888_spi_rw_array ? */
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ret = tle8888_spi_rw(chip, CMD_OPSTAT1, NULL);
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if (ret)
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/* request OutDiad0, ignore received */
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if ((ret = tle8888_spi_rw(chip, CMD_OUTDIAG(0), NULL)))
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return ret;
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ret = tle8888_spi_rw(chip, CMD_OPSTAT1, &rx);
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if (ret)
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/* request OutDiad1, receive OutDiag0 */
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if ((ret = tle8888_spi_rw(chip, CMD_OUTDIAG(1), &rx)))
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return ret;
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chip->OutDiag[0] = getDataFromResponse(rx);
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// available in debugFloatField3
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chip->OpStat[1] = rx;
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/* request OutDiad2, receive OutDiag1 */
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if ((ret = tle8888_spi_rw(chip, CMD_OUTDIAG(2), &rx)))
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return ret;
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chip->OutDiag[1] = getDataFromResponse(rx);
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/* request OutDiad3, receive OutDiag2 */
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if ((ret = tle8888_spi_rw(chip, CMD_OUTDIAG(3), &rx)))
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return ret;
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chip->OutDiag[2] = getDataFromResponse(rx);
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/* request OutDiad4, receive OutDiag3 */
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if ((ret = tle8888_spi_rw(chip, CMD_OUTDIAG(4), &rx)))
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return ret;
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chip->OutDiag[3] = getDataFromResponse(rx);
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/* request BriDiag0, receive OutDiag4 */
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if ((ret = tle8888_spi_rw(chip, CMD_BRIDIAG(0), &rx)))
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return ret;
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chip->OutDiag[4] = getDataFromResponse(rx);
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/* request BriDiag1, receive BriDiag0 */
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if ((ret = tle8888_spi_rw(chip, CMD_BRIDIAG(1), &rx)))
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return ret;
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chip->BriDiag[0] = getDataFromResponse(rx);
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/* request IgnDiag, receive BriDiag1 */
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if ((ret = tle8888_spi_rw(chip, CMD_IGNDIAG, &rx)))
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return ret;
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chip->BriDiag[1] = getDataFromResponse(rx);
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/* request OpStat0, receive IgnDiag */
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if ((ret = tle8888_spi_rw(chip, CMD_OPSTAT(0), &rx)))
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return ret;
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chip->IgnDiag = getDataFromResponse(rx);
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/* request OpStat1, receive OpStat0 */
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if ((ret = tle8888_spi_rw(chip, CMD_OPSTAT(1), &rx)))
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return ret;
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chip->OpStat[0] = getDataFromResponse(rx);
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/* request OpStat1, receive OpStat1 */
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if ((ret = tle8888_spi_rw(chip, CMD_OPSTAT(1), &rx)))
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return ret;
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chip->OpStat[1] = getDataFromResponse(rx);
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/* TODO: unlock? */
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@ -452,6 +543,9 @@ int startupConfiguration(struct tle8888_priv *chip) {
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chip->o_direct_mask = 0;
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chip->o_oe_mask = 0;
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/* HACK HERE if you want to enable PP for OUT21..OUT24
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* without approprirate call to setPinMode */
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chip->o_pp_mask = 0; /* = BIT(20) | BIT(21) | BIT(22) | BIT(23); */
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/* enable direct drive of OUTPUT4..1
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* ...still need INJEN signal */
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chip->o_direct_mask |= 0x0000000f;
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@ -533,7 +627,7 @@ void watchdogLogic(struct tle8888_priv *chip) {
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tle8888_spi_rw(chip, CMD_FWDSTAT1, &maybeFirstResponse);
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// here we get response of the 'FWDStat1' above
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tle8888_spi_rw(chip, CMD_WdDiag, &functionWDrx);
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handleFWDStat1(chip, getRegisterFromResponse(functionWDrx), (functionWDrx >> 8) & 0xff);
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handleFWDStat1(chip, getRegisterFromResponse(functionWDrx), getDataFromResponse(functionWDrx));
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lastFunctionWatchdogTimeNt = nowNt;
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}
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@ -603,9 +697,14 @@ static THD_FUNCTION(tle8888_driver_thread, p) {
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/* set state to TLE8888_FAILED? */
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}
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ret = tle8888_update_status(chip);
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if (ret) {
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/* set state to TLE8888_FAILED or force reinit? */
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if (chVTTimeElapsedSinceX(chip->ts_diag) >= TIME_MS2I(TLE8888_POLL_INTERVAL_MS)) {
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/* this is expensive call, will do a lot of spi transfers... */
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ret = tle8888_update_status_and_diag(chip);
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if (ret) {
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/* set state to TLE8888_FAILED or force reinit? */
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}
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chip->ts_diag = chVTGetSystemTimeX();
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}
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/* if bit OE is cleared - reset happened */
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@ -630,6 +729,32 @@ void requestTLE8888initialization(void) {
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/* Driver exported functions. */
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/*==========================================================================*/
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static int tle8888_setPadMode(void *data, unsigned int pin, iomode_t mode) {
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if ((pin >= TLE8888_OUTPUTS) || (data == NULL))
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return -1;
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/* do not enalbe PP mode yet */
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#if 0
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struct tle8888_priv *chip = (struct tle8888_priv *)data;
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/* only OUT21..OUT24 support mode change: PP vs OD */
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if ((pin < 20) || (pin > 23))
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return 0;
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/* this is absolutly confusing... we pass STM32 specific
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* values to tle8888 driver... But this is how gpios
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* currently implemented */
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if ((mode & PAL_STM32_OTYPE_MASK) == PAL_STM32_OTYPE_OPENDRAIN) {
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chip->o_pp_mask &= ~BIT(pin);
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} else {
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chip->o_pp_mask |= BIT(pin);
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}
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#endif
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return 0;
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}
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static int tle8888_writePad(void *data, unsigned int pin, int value) {
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if ((pin >= TLE8888_OUTPUTS) || (data == NULL))
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@ -653,6 +778,74 @@ static int tle8888_writePad(void *data, unsigned int pin, int value) {
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return 0;
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}
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static brain_pin_diag_e tle8888_2b_to_diag_no_temp(unsigned int bits)
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{
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if (bits == 0x01)
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return PIN_SHORT_TO_BAT;
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if (bits == 0x02)
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return PIN_OPEN;
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if (bits == 0x03)
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return PIN_SHORT_TO_GND;
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return PIN_OK;
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}
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static brain_pin_diag_e tle8888_2b_to_diag_with_temp(unsigned int bits)
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{
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brain_pin_diag_e diag = tle8888_2b_to_diag_no_temp(bits);
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if (diag == PIN_SHORT_TO_BAT)
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diag |= PIN_DRIVER_OVERTEMP;
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return diag;
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}
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static brain_pin_diag_e tle8888_getDiag(void *data, unsigned int pin)
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{
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if ((pin >= TLE8888_OUTPUTS) || (data == NULL))
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return PIN_INVALID;
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struct tle8888_priv *chip = (struct tle8888_priv *)data;
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if (pin < 4)
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return tle8888_2b_to_diag_with_temp((chip->OutDiag[0] >> ((pin - 0) * 2)) & 0x03);
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if (pin < 8) {
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if (pin == 7)
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return tle8888_2b_to_diag_no_temp((chip->OutDiag[1] >> ((pin - 4) * 2)) & 0x03);
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else
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return tle8888_2b_to_diag_with_temp((chip->OutDiag[1] >> ((pin - 4) * 2)) & 0x03);
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}
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if (pin < 12)
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return tle8888_2b_to_diag_with_temp((chip->OutDiag[2] >> ((pin - 8) * 2)) & 0x03);
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if (pin < 16) {
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if (pin == 12)
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return tle8888_2b_to_diag_no_temp((chip->OutDiag[3] >> ((pin - 12) * 2)) & 0x03);
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else
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return tle8888_2b_to_diag_with_temp((chip->OutDiag[3] >> ((pin - 12) * 2)) & 0x03);
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}
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if (pin < 20)
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return tle8888_2b_to_diag_with_temp((chip->OutDiag[4] >> ((pin - 16) * 2)) & 0x03);
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if (pin < 24) {
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/* half bridges */
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brain_pin_diag_e diag;
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diag = tle8888_2b_to_diag_no_temp((chip->BriDiag[0] >> ((pin - 20) * 2)) & 0x03);
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if (((pin == 22) || (pin == 23)) &&
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(chip->BriDiag[1] & BIT(5)))
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diag |= PIN_DRIVER_OVERTEMP;
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if (((pin == 20) || (pin == 21)) &&
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(chip->BriDiag[1] & BIT(4)))
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diag |= PIN_DRIVER_OVERTEMP;
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if (chip->BriDiag[1] & BIT(pin - 20))
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diag |= PIN_OVERLOAD; /* overcurrent */
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return diag;
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}
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if (pin < 28)
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return tle8888_2b_to_diag_with_temp((chip->IgnDiag >> ((pin - 24) * 2)) & 0x03);
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return PIN_OK;
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}
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/**
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* @return 0 for valid configuration, -1 for invalid configuration
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*/
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@ -689,10 +882,10 @@ int tle8888SpiStartupExchange(struct tle8888_priv *chip) {
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startupConfiguration(chip);
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if (CONFIG(verboseTLE8888)) {
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tle8888_dump_regs();
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}
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return 0;
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}
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@ -772,9 +965,10 @@ static int tle8888_deinit(void *data)
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}
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struct gpiochip_ops tle8888_ops = {
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.setPadMode = tle8888_setPadMode,
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.writePad = tle8888_writePad,
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.readPad = NULL, /* chip outputs only */
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//.getDiag = tle8888_getDiag,
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.getDiag = tle8888_getDiag,
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.init = tle8888_init,
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.deinit = tle8888_deinit,
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};
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