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134 connector draft

This commit is contained in:
rusefi 2019-11-02 09:29:54 -04:00
parent 5fd03a9f92
commit 9a1e18c1b0
5 changed files with 10595 additions and 0 deletions
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5895
hardware/Breakout_134pin_7-967288-1/134pin_7-967288-1.kicad_pcb Normal file
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hardware/Breakout_134pin_7-967288-1/134pin_7-967288-1.pro Normal file
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update=9/29/2019 5:18:38 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=rusefi_lib_external/Border.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=rusefi_lib_external/Border.kicad_wks
LastNetListRead=microRusEfi.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2032
MinViaDiameter=0.2
MinViaDrill=0.3
MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127
MinHoleToHole=0.25
TrackWidth1=0.2032
TrackWidth2=0.2032
TrackWidth3=0.2159
TrackWidth4=0.2159
TrackWidth5=0.3048
TrackWidth6=0.4064
TrackWidth7=0.55
TrackWidth8=0.6
TrackWidth9=1.0668
TrackWidth10=1.651
TrackWidth11=1.6764
TrackWidth12=2.7178
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.78994
ViaDrill3=0.43434
ViaDiameter4=1
ViaDrill4=0.5
ViaDiameter5=1.54178
ViaDrill5=1.18618
dPairWidth1=0.2032
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.25
SilkTextSizeV=0.75
SilkTextSizeH=0.75
SilkTextSizeThickness=0.13
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.2
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=7.599999999999999e-05
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.2032
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=1A EXTERNAL
Clearance=0.1905
TrackWidth=0.3048
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=2.5A EXTERNAL
Clearance=0.1905
TrackWidth=1.0668
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=3,5A EXT HIGH VOLTAGE
Clearance=1.016
TrackWidth=1.6764
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=3.5A EXTERNAL
Clearance=0.1905
TrackWidth=1.651
ViaDiameter=1.0922
ViaDrill=0.6858
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/5]
Name=5A EXTERNAL
Clearance=0.2159
TrackWidth=1.0668
ViaDiameter=1.54178
ViaDrill=1.18618
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/6]
Name=CUSTOM
Clearance=0.1524
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/7]
Name=CUSTOM 0.6
Clearance=0.1524
TrackWidth=0.6
ViaDiameter=1
ViaDrill=0.4
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/8]
Name=MIN_EXTERN_188A
Clearance=0.1524
TrackWidth=0.2032
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/9]
Name=MIN_EXTERN_241A
Clearance=0.1524
TrackWidth=0.2159
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25

47
hardware/Breakout_134pin_7-967288-1/134pin_7-967288-1.sch Normal file
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EESchema Schematic File Version 4
LIBS:134pin_7-967288-1-cache
EELAYER 30 0
EELAYER END
$Descr A 11000 8500
encoding utf-8
Sheet 1 1
Title "Breakout board"
Date "2019-10-14"
Rev "R0.1"
Comp "rusEFI.com"
Comment1 "Donald Becker"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Graphic:Logo_Open_Hardware_Small LOGO1
U 1 1 5D21BC70
P 5975 7725
F 0 "LOGO1" H 5975 8000 50 0001 C CNN
F 1 "DNP" H 5975 7500 50 0001 C CNN
F 2 "rusEFI:LogoMRE" H 5975 7725 50 0001 C CNN
F 3 "~" H 5975 7725 50 0001 C CNN
F 4 "DNP" H -5915 -2520 50 0001 C CNN "Part #"
F 5 "DNP" H -5915 -2520 50 0001 C CNN "VEND"
F 6 "DNP" H -5915 -2520 50 0001 C CNN "VEND#"
F 7 "DNP" H -5915 -2520 50 0001 C CNN "Manufacturer"
1 5975 7725
1 0 0 -1
$EndComp
$Comp
L microRusEfi-rescue:LOGO-rusefi_Logo LOGO2
U 1 1 5D54AA23
P 5475 7725
F 0 "LOGO2" H 5475 8000 50 0001 C CNN
F 1 "DNP" H 5475 7500 50 0001 C CNN
F 2 "rusEFI:LOGO" H 5475 7725 50 0001 C CNN
F 3 "~" H 5475 7725 50 0001 C CNN
F 4 "DNP" H -6415 -2520 50 0001 C CNN "Part #"
F 5 "DNP" H -6415 -2520 50 0001 C CNN "VEND"
F 6 "DNP" H -6415 -2520 50 0001 C CNN "VEND#"
F 7 "DNP" H -6415 -2520 50 0001 C CNN "Manufacturer"
1 5475 7725
1 0 0 -1
$EndComp
$EndSCHEMATC

4283
hardware/Breakout_134pin_7-967288-1/Project_Specific_Libs/Breakout_134pin_7-967288-1_KC5.pretty/7-967288-1_134-pin-connector.kicad_mod Normal file
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hardware/Breakout_134pin_7-967288-1/fp-lib-table Normal file
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(fp_lib_table
(lib (name rusEFI)(type KiCad)(uri ${KIPRJMOD}/../rusefi_lib/rusefi_lib.pretty)(options "")(descr ""))
(lib (name Breakout_134pin_7-967288-1_KC5)(type KiCad)(uri ${KIPRJMOD}/Project_Specific_Libs/Breakout_134pin_7-967288-1_KC5.pretty)(options "")(descr ""))
)