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a7c7d3dcac
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@ -151,8 +151,6 @@ static const struct mc33810_config mc33810 = {
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// ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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// ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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((0b110 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 128 */
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((0b110 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 128 */
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SPI_CR1_MSTR |
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SPI_CR1_MSTR |
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/* SPI_CR1_CPOL | */ // = 0
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SPI_CR1_CPHA | // = 1
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0,
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0,
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.cr2 = SPI_CR2_16BIT_MODE
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.cr2 = SPI_CR2_16BIT_MODE
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},
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},
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@ -240,7 +240,10 @@ static const struct mc33810_config mc33810_odd = {
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((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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SPI_CR1_MSTR |
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SPI_CR1_MSTR |
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/* SPI_CR1_CPOL | */ // = 0
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/* SPI_CR1_CPOL | */ // = 0
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/*
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https://github.com/rusefi/rusefi/issues/6538 says that should be zero
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SPI_CR1_CPHA | // = 1
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SPI_CR1_CPHA | // = 1
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*/
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0,
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0,
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.cr2 = //SPI_CR2_16BIT_MODE |
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.cr2 = //SPI_CR2_16BIT_MODE |
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SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
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SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
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@ -276,7 +279,10 @@ static const struct mc33810_config mc33810_even = {
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((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | /* div = 16 */
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SPI_CR1_MSTR |
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SPI_CR1_MSTR |
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/* SPI_CR1_CPOL | */ // = 0
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/* SPI_CR1_CPOL | */ // = 0
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/*
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https://github.com/rusefi/rusefi/issues/6538 says that should be zero
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SPI_CR1_CPHA | // = 1
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SPI_CR1_CPHA | // = 1
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*/
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0,
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0,
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.cr2 = SPI_CR2_16BIT_MODE
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.cr2 = SPI_CR2_16BIT_MODE
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},
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},
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