TLE8888: initial support (#733)
This commit is contained in:
dron0gus
rusefi
parent
be926cb792
commit
bb0fcf3f87
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@ -9,8 +9,7 @@ HW_LAYER_DRIVERS_CORE = \
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HW_LAYER_DRIVERS = \
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$(DRIVERS_DIR)/gpio/tle6240.c \
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$(DRIVERS_DIR)/gpio/tle8888.c
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HW_LAYER_DRIVERS_CPP =
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HW_LAYER_DRIVERS_CPP = \
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$(DRIVERS_DIR)/gpio/tle8888.cpp \
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@ -0,0 +1,290 @@
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/*
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* tle8888.c
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*
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* TLE8888 Engine Machine System IC driver
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*
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* @date Mar 25, 2019
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* @author Andrey Belomutskiy, (c) 2012-2019
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*
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* Andrey Gusakov, (c) 2019
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*/
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/* to be removed */
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#include "engine_configuration.h"
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#include "global.h"
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#include "gpio/gpio_ext.h"
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#include "gpio/tle8888.h"
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#include "pin_repository.h"
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/* TODO: move to board.h file */
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#define BOARD_TLE8888_COUNT 1
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#ifndef BOARD_TLE8888_COUNT
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#define BOARD_TLE8888_COUNT 0
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#endif
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#if (BOARD_TLE8888_COUNT > 0)
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/*
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* TODO list:
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*/
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/*==========================================================================*/
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/* Driver local definitions. */
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/*==========================================================================*/
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#define DRIVER_NAME "tle8888"
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/*==========================================================================*/
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/* Driver exported variables. */
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/*==========================================================================*/
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/* C0 */
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#define CMD_READ (0 << 0)
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#define CMD_WRITE (1 << 0)
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/* C7:1 */
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#define CMD_REG_ADDR(a) (((a) & 0x7f) << 1)
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/* CD7:0 */
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#define CMD_REG_DATA(d) (((d) & 0xff) << 8)
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#define CMD_WR(a, d) (CMD_WRITE | CMD_REG_ADDR(a) | CMD_REG_DATA(d))
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#define CMD_SR CMD_WR(0x1a, 0x03)
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#define CMD_OE_SET CMD_WR(0x1c, 0x02)
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#define CMD_OE_CLR CMD_WR(0x1c, 0x01)
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#define CMD_LOCK CMD_WR(0x1e, 0x02)
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#define CMD_UNLOCK CMD_WR(0x1e, 0x01)
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#define CMD_INCONFIG(n, d) CMD_WR(0x53 + (n & 0x03), d)
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#define CMD_DDCONFIG(n, d) CMD_WR(0x57 + (n & 0x03), d)
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#define CMD_OECONFIG(n, d) CMD_WR(0x5b + (n & 0x03), d)
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/*==========================================================================*/
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/* Driver local variables and types. */
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/*==========================================================================*/
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/* Driver private data */
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struct tle8888_priv {
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const struct tle8888_config *cfg;
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};
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static struct tle8888_priv chips[BOARD_TLE8888_COUNT];
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/*==========================================================================*/
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/* Driver local functions. */
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/*==========================================================================*/
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static SPIDriver *get_bus(struct tle8888_priv *chip)
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{
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/* return non-const SPIDriver* from const struct cfg */
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return chip->cfg->spi_bus;
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}
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static int tle8888_spi_rw(struct tle8888_priv *chip, uint16_t tx, uint16_t *rx)
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{
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uint16_t rxb;
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SPIDriver *spi = get_bus(chip);
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/**
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* 15.1 SPI Protocol
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*
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* after a read or write command: the address and content of the selected register
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* is transmitted with the next SPI transmission (for not existing addresses or
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* wrong access mode the data is always 0)
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*/
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/* Acquire ownership of the bus. */
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spiAcquireBus(spi);
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/* Setup transfer parameters. */
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spiStart(spi, &chip->cfg->spi_config);
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/* Slave Select assertion. */
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spiSelect(spi);
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/* Atomic transfer operations. */
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rxb = spiPolledExchange(spi, tx);
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/* Slave Select de-assertion. */
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spiUnselect(spi);
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/* Ownership release. */
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spiReleaseBus(spi);
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if (rx)
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*rx = rxb;
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/* no errors for now */
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return 0;
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}
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/*==========================================================================*/
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/* Driver thread. */
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/*==========================================================================*/
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/*==========================================================================*/
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/* Driver interrupt handlers. */
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/*==========================================================================*/
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/*==========================================================================*/
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/* Driver exported functions. */
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/*==========================================================================*/
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int tle8888_chip_init(void * data)
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{
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int i;
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int ret;
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struct tle8888_priv *chip = (struct tle8888_priv *)data;
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const struct tle8888_config *cfg = chip->cfg;
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uint8_t dd[4] = {0, 0, 0, 0};
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uint8_t oe[4] = {0, 0, 0, 0};
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/* mark pins used */
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ret = markUsed(cfg->spi_config.ssport, cfg->spi_config.sspad, DRIVER_NAME " CS");
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if (cfg->reset.port != NULL)
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ret |= markUsed(cfg->reset.port, cfg->reset.pad, DRIVER_NAME " RST");
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for (i = 0; i < TLE8888_DIRECT_OUTPUTS; i++)
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if (cfg->direct_io[i].port)
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ret |= markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, DRIVER_NAME " DIRECT IO");
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if (ret) {
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ret = -1;
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goto err_gpios;
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}
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/* Software reset */
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tle8888_spi_rw(chip, CMD_SR, NULL);
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/* delay? */
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/* Set LOCK bit to 0 */
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tle8888_spi_rw(chip, CMD_UNLOCK, NULL);
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/* enable direct drive of OUTPUT4..1
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* ...still need INJEN signal */
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dd[0] |= 0x0f;
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oe[0] |= 0x0f;
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/* enable direct drive of IGN4..1
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* ...still need IGNEN signal */
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dd[3] |= 0x0f;
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oe[3] |= 0x0f;
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/* map and enable outputs for direct driven channels */
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for (i = 0; i < TLE8888_DIRECT_MISC; i++) {
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int reg;
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int mask;
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int out = cfg->direct_map[i];
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/* OUT1..4 driven direct only */
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if (out < 5)
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return -1;
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reg = (out - 1)/ 8;
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mask = 1 << ((out - 1) % 8);
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/* check if output already ocupied */
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if (dd[reg] & mask) {
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/* incorrect config? */
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return -1;
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}
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/* enable direct drive and output enable */
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dd[reg] |= mask;
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oe[reg] |= mask;
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tle8888_spi_rw(chip, CMD_INCONFIG(reg, out - 5), NULL);
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}
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/* set registers */
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for (i = 0; i < 4; i++) {
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tle8888_spi_rw(chip, CMD_OECONFIG(i, oe[i]), NULL);
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tle8888_spi_rw(chip, CMD_DDCONFIG(i, dd[i]), NULL);
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}
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/* enable outputs */
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tle8888_spi_rw(chip, CMD_OE_SET, NULL);
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err_gpios:
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/* unmark pins */
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markUnused(cfg->spi_config.ssport, cfg->spi_config.sspad);
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if (cfg->reset.port != NULL)
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markUnused(cfg->reset.port, cfg->reset.pad);
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for (i = 0; i < TLE8888_DIRECT_OUTPUTS; i++)
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if (cfg->direct_io[i].port)
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markUnused(cfg->direct_io[i].port, cfg->direct_io[i].pad);
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return ret;
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}
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/**
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* @brief TLE8888 driver add.
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* @details Checks for valid config
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*/
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int tle8888_add(unsigned int index, const struct tle8888_config *cfg)
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{
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struct tle8888_priv *chip;
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/* no config or no such chip */
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osalDbgCheck((cfg != NULL) && (cfg->spi_bus != NULL) && (index < BOARD_TLE8888_COUNT));
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/* check for valid cs.
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* DOTO: remove this check? CS can be driven by SPI */
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if (cfg->spi_config.ssport == NULL)
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return -1;
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chip = &chips[index];
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/* already initted? */
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if (chip->cfg != NULL)
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return -1;
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/* TODO: remove this when gpiochips integrated */
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return tle8888_chip_init(chip);
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}
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#else /* BOARD_TLE8888_COUNT > 0 */
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int tle8888_add(unsigned int index, const struct tle8888_config *cfg)
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{
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(void)index; (void)cfg;
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return -1;
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}
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#endif /* BOARD_TLE8888_COUNT */
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/*********TO BE REMOVED FROM THIS FILE***************/
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/* this should be in board file */
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static const struct tle8888_config tle8888_cfg = {
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.spi_bus = &SPID4,
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.spi_config = {
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.circular = false,
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.end_cb = NULL,
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.ssport = GPIOF,
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.sspad = 0U,
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.cr1 =
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/* TODO: set LSB first mode !!!! */
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/* SPI_CR1_CPOL | */ // = 0
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SPI_CR1_CPHA | // = 1
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(((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
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SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
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/* 16-bit transfer */
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.cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
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},
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/* not implemented yet, use STM32 gpios directly */
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.direct_io = {
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[0] = {.port = NULL},
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[1] = {.port = NULL},
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[2] = {.port = NULL},
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[3] = {.port = NULL},
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},
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.direct_map = {
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/* to be fixed */
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9, 10, 11, 12
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},
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};
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void initTle8888(DECLARE_ENGINE_PARAMETER_SIGNATURE)
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{
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tle8888_add(0, &tle8888_cfg);
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}
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/*********TO BE REMOVED FROM THIS FILE ENDS***********/
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@ -1,86 +0,0 @@
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/**
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*
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* TLE8888 driver
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*
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* at the moment only Enable Outputs is implemented - this command is needed to get parallel control pins
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*
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* @date Mar 25, 2019
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* @author Andrey Belomutskiy, (c) 2012-2019
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*/
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#include "engine.h"
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#include "tle8888.h"
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#include "hardware.h"
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#if EFI_TLE8888 || defined(__DOXYGEN__)
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/**
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* 15.2 SPI Frame Definition
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*
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*/
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#define Cmd_write_access 1
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#define CmdOE 0x1C
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#define DATA_OE_ENABLE 0b00000010
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static unsigned char tx_buff[2];
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static unsigned char rx_buff[2];
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extern TunerStudioOutputChannels tsOutputChannels;
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EXTERN_ENGINE;
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static SPIDriver *driver;
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static OutputPin tle8888Cs;
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static SPIConfig spiConfig = { /* end_cb */ NULL,
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/* HW dependent part.*/
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/* ssport */ NULL, /* sspad */ 0, /* cr1 */ SPI_CR1_MSTR | SPI_CR1_CPHA, /* cr2*/ 0 };
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void initTle8888(DECLARE_ENGINE_PARAMETER_SIGNATURE) {
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if (engineConfiguration->tle8888_cs == GPIO_UNASSIGNED) {
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return;
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}
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// SPI pins are enabled in initSpiModules()
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tle8888Cs.initPin("tle8888 CS", engineConfiguration->tle8888_cs,
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&engineConfiguration->tle8888_csPinMode);
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spiConfig.cr1 += getSpiPrescaler(_150KHz, engineConfiguration->tle8888spiDevice);
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driver = getSpiDevice(engineConfiguration->tle8888spiDevice);
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if (driver == NULL) {
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// error already reported
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return;
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}
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// todo: reuse initSpiCs method?
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spiConfig.ssport = getHwPort("tle8888", engineConfiguration->tle8888_cs);
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spiConfig.sspad = getHwPin("tle8888", engineConfiguration->tle8888_cs);
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spiStart(driver, &spiConfig);
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tx_buff[0] = Cmd_write_access + CmdOE;
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tx_buff[1] = DATA_OE_ENABLE;
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// todo: extract 'sendSync' method?
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spiSelect(driver);
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spiSend(driver, 2, tx_buff);
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if (engineConfiguration->debugMode == DBG_TLE8888) {
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tsOutputChannels.debugIntField1 = 2;
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}
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/**
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* 15.1 SPI Protocol
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*
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* after a read or write command: the address and content of the selected register
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* is transmitted with the next SPI transmission (for not existing addresses or
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* wrong access mode the data is always “0”)
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*/
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spiReceive(driver, 2, rx_buff);
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if (engineConfiguration->debugMode == DBG_TLE8888) {
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tsOutputChannels.debugIntField2 = (rx_buff[1] << 8) + rx_buff[0];
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}
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spiUnselect(driver);
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}
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#endif /* EFI_TLE8888 */
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@ -10,6 +10,49 @@
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#include "global.h"
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#include <hal.h>
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#define TLE8888_OUTPUTS 20 /* ? */
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/* 4 misc channels */
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#define TLE8888_DIRECT_MISC 4
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/* 4 IGN channels - INJ1..4 - IN1..4
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* 4 INJ channels - OUT1..4 - IN5..8 */
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#define TLE8888_DIRECT_OUTPUTS (4 + 4 + TLE8888_DIRECT_MISC)
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/* DOTO: add irq support */
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#define TLE8888_POLL_INTERVAL_MS 100
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/* note that spi transfer should be LSB first */
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struct tle8888_config {
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SPIDriver *spi_bus;
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const SPIConfig spi_config;
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/* bidirectional, check DS */
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struct {
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ioportid_t port;
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uint_fast8_t pad;
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} reset;
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/* currently not used.
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* TODO: update as it is done in TLE6240 */
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struct {
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ioportid_t port;
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uint_fast8_t pad;
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} direct_io[TLE8888_DIRECT_MISC];
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/* maping array for IN9..12, output numbers starts from 1, as in DS */
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uint8_t direct_map[TLE8888_DIRECT_MISC];
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};
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#ifdef __cplusplus
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extern "C"
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{
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#endif /* __cplusplus */
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/* cleanup !!!! */
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void initTle8888(DECLARE_ENGINE_PARAMETER_SIGNATURE);
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int tle8888_add(unsigned int index, const struct tle8888_config *cfg);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* HW_LAYER_DRIVERS_GPIO_TLE8888_H_ */
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