From bd0e04669aef7f715096a1846c535096544e7874 Mon Sep 17 00:00:00 2001 From: rusefi Date: Fri, 24 Jan 2025 22:19:47 -0500 Subject: [PATCH] CORE_CLOCK replacement progress --- firmware/development/rfi_perftest.cpp | 2 +- firmware/hw_layer/drivers/sent/sent_hw_icu.cpp | 2 +- firmware/hw_layer/ports/cypress/port_mpu_util.h | 4 ++-- firmware/hw_layer/ports/kinetis/port_mpu_util.h | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/firmware/development/rfi_perftest.cpp b/firmware/development/rfi_perftest.cpp index 0e4fb54a15..15b8970fc9 100644 --- a/firmware/development/rfi_perftest.cpp +++ b/firmware/development/rfi_perftest.cpp @@ -264,7 +264,7 @@ static int rtcStartTime; static void timeInfo() { efiPrintf("chTimeNow as seconds = %d", getTimeNowS()); - efiPrintf("hal seconds = %d", halTime.get() / (long)CORE_CLOCK); + efiPrintf("hal seconds = %d", halTime.get() / (long)STM32_SYSCLK); #if EFI_RTC int unix = rtcGetTimeUnixSec(&RTCD1) - rtcStartTime; diff --git a/firmware/hw_layer/drivers/sent/sent_hw_icu.cpp b/firmware/hw_layer/drivers/sent/sent_hw_icu.cpp index dbbfe1749c..9b0e40d03a 100644 --- a/firmware/hw_layer/drivers/sent/sent_hw_icu.cpp +++ b/firmware/hw_layer/drivers/sent/sent_hw_icu.cpp @@ -26,7 +26,7 @@ /* TODO: get at runtime */ /* Max timer clock for most timers on STM32 is CPU clock / 2 */ #define SENT_TIMER_CLOCK_DIV 2 -#define SENT_ICU_FREQ (CORE_CLOCK / SENT_TIMER_CLOCK_DIV) // == CPU freq / 2 +#define SENT_ICU_FREQ (STM32_SYSCLK / SENT_TIMER_CLOCK_DIV) // == CPU freq / 2 static uint16_t lastPulse[SENT_INPUT_COUNT]; static bool overcapture[SENT_INPUT_COUNT]; diff --git a/firmware/hw_layer/ports/cypress/port_mpu_util.h b/firmware/hw_layer/ports/cypress/port_mpu_util.h index c486a51ee6..3eeb2b983a 100644 --- a/firmware/hw_layer/ports/cypress/port_mpu_util.h +++ b/firmware/hw_layer/ports/cypress/port_mpu_util.h @@ -10,8 +10,8 @@ #define PORT_SIZE 16 -// todo: stm32 ticks are based on 4MHz timer I wonder if these CORE_CLOCK-based clocks are broken here?! -#define US_TO_NT_MULTIPLIER (CORE_CLOCK / 1000000) +// todo: stm32 ticks are based on 4MHz timer I wonder if these STM32_SYSCLK-based clocks are broken here?! +#define US_TO_NT_MULTIPLIER (STM32_SYSCLK / 1000000) // Scheduler queue GPT device #define GPTDEVICE GPTD1 diff --git a/firmware/hw_layer/ports/kinetis/port_mpu_util.h b/firmware/hw_layer/ports/kinetis/port_mpu_util.h index 9773087a06..5b45aeae4b 100644 --- a/firmware/hw_layer/ports/kinetis/port_mpu_util.h +++ b/firmware/hw_layer/ports/kinetis/port_mpu_util.h @@ -11,8 +11,8 @@ // This is the radical departure from STM32 #define PORT_SIZE 18 -// todo: stm32 ticks are based on 4MHz timer I wonder if these CORE_CLOCK-based clocks are broken here?! -#define US_TO_NT_MULTIPLIER (CORE_CLOCK / 1000000) +// todo: stm32 ticks are based on 4MHz timer I wonder if these STM32_SYSCLK-based clocks are broken here?! +#define US_TO_NT_MULTIPLIER (STM32_SYSCLK / 1000000) // Scheduler queue GPT device #define GPTDEVICE GPTD1