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Reset Cause for H7

This commit is contained in:
andreika-git 2023-12-13 14:41:36 +02:00 committed by rusefillc
parent a64fda548f
commit bdbebeef55
1 changed files with 29 additions and 6 deletions
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35
firmware/hw_layer/ports/stm32/stm32_reset_cause.cpp
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@ -13,23 +13,46 @@
#include "mpu_util.h"
#endif /* EFI_PROD_CODE */
#ifdef STM32H7XX
// Reset Status Register flags for H7
#define IWDGRSTF RCC_RSR_IWDG1RSTF
#define WWDGRSTF RCC_RSR_WWDG1RSTF
#define SFTRSTF RCC_RSR_SFTRSTF
#define PINRSTF RCC_RSR_PINRSTF
#define LPWRRSTF RCC_RSR_LPWRRSTF
#define BORRSTF RCC_RSR_BORRSTF
#else
// Control/Status Register flags for F4/F7
#define IWDGRSTF RCC_CSR_IWDGRSTF
#define WWDGRSTF RCC_CSR_WWDGRSTF
#define SFTRSTF RCC_CSR_SFTRSTF
#define PINRSTF RCC_CSR_PINRSTF
#define LPWRRSTF RCC_CSR_LPWRRSTF
#define BORRSTF RCC_CSR_BORRSTF
#endif // STM32H7XX
static Reset_Cause_t readMCUResetCause() {
#ifdef STM32H7XX
uint32_t cause = RCC->RSR; // Read the Reset Status Register
// Clear reset flags for future reset detection
RCC->RSR |= RCC_RSR_RMVF;
#else
uint32_t cause = RCC->CSR; // Read the Control/Status Register
// Clear reset flags for future reset detection
RCC->CSR |= RCC_CSR_RMVF;
#endif
if (cause & RCC_CSR_IWDGRSTF) {
if (cause & IWDGRSTF) {
return Reset_Cause_IWatchdog;
} else if (cause & RCC_CSR_WWDGRSTF) {
} else if (cause & WWDGRSTF) {
return Reset_Cause_WWatchdog;
} else if (cause & RCC_CSR_SFTRSTF) {
} else if (cause & SFTRSTF) {
return Reset_Cause_Soft_Reset;
} else if (cause & RCC_CSR_PINRSTF) {
} else if (cause & PINRSTF) {
return Reset_Cause_NRST_Pin;
} else if (cause & RCC_CSR_LPWRRSTF) {
} else if (cause & LPWRRSTF) {
return Reset_Cause_Illegal_Mode;
} else if (cause & RCC_CSR_BORRSTF) {
} else if (cause & BORRSTF) {
return Reset_Cause_BOR;
}
return Reset_Cause_Unknown;