diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml index cd2add6f00..7c4de78a7e 100644 --- a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml @@ -10,7 +10,17 @@ ARM 32-bit Cortex-M4 based device - + + + + + + + + + + + @@ -42,9 +52,43 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE - + + + + + Single + 0x4 + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml index 263c13a704..d44fd506fb 100644 --- a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml @@ -232,7 +232,7 @@ - WRP0 + nWRP0 0x10 0x8 @@ -243,7 +243,7 @@ - WRP0 + nWRP0 0x10 0x8 @@ -363,10 +363,10 @@ Write Protection - + - WRP0 + nWRP0 0x0 0x8 @@ -377,7 +377,7 @@ - WRP0 + nWRP0 0x0 0x8 diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml index fb2abf03cd..491e6b6d5e 100644 --- a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml @@ -187,7 +187,7 @@ - WRP bit0 + WRP_bit0 0x0 0x8 @@ -198,7 +198,7 @@ - nWRP bit8 + nWRP_bit8 0x10 0x8 diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml index 7611df87c3..d7e75dab8d 100644 --- a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml @@ -11,26 +11,8 @@ - - - - - - - - - - - - - - - - - - - + @@ -39,7 +21,7 @@ - + @@ -47,6 +29,24 @@ + + + + + + + + + + + + + + + + + + @@ -62,13 +62,23 @@ - + + + + + + + + + + + - - + + @@ -105,7 +115,7 @@ - + Single @@ -123,7 +133,7 @@ - + Dual @@ -152,7 +162,7 @@ - + Single @@ -170,7 +180,7 @@ - + Dual @@ -207,7 +217,7 @@ 0xFF RWE - + Single @@ -225,7 +235,7 @@ - + Dual diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml index 222aedff40..05548df250 100644 --- a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml @@ -47,1767 +47,13 @@ - OTP + Struct version - + - none - none - 0x0 - 0x20 - R - - - - - - - - TR - set SAFMEM Ring current level, default value = 0b00 - 0x7 - 0x2 - RW - - - PRGWIDTH - SAFMEM Programming Pulse Width, default value = 0b0001 - 0x3 - 0x4 - RW - - - FRC - SAFMEM CLOCK frequency range selection, default value = 0b11 - 0x1 - 0x2 - RW - - - PWRUP - SAFMEM Power up control - 0x0 - 0x1 - RW - - - - - - - - BIST2LOCK - 0: BIST2 is not locked, 1: BIST2 is locked. - 0x7 - 0x1 - R - - - BIST1LOCK - 0: BIST1 is not locked, 1: BIST1 is locked. - 0x6 - 0x1 - R - - - PWRON - 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. - 0x5 - 0x1 - R - - - PROGFAIL - 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. - 0x4 - 0x1 - R - - - BUSY - 0: SAFMEM is Idle, 1: SAFMEM operation is on going. - 0x3 - 0x1 - R - - - INVALID - 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. - 0x2 - 0x1 - R - - - FULLDBG - 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. - 0x1 - 0x1 - R - - - SECURE - 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. - 0x0 - 0x1 - R - - - - - - - - GPLOCK - 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. - 0x4 - 0x1 - RW - - - FENREG - 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. - 0x3 - 0x1 - RW - - - DENREG - 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. - 0x2 - 0x1 - RW - - - OTP - 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. - 0x0 - 0x1 - RW - - - - - - - - DBGSWENABLE - Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. - 0xA - 0x1 - RW - - - CFGSDISABLE - Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. - 0x9 - 0x1 - RW - - - CP15SDISABLE - Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. - 0x7 - 0x2 - RW - - - SPNIDEN - Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. - 0x6 - 0x1 - RW - - - SPIDEN - Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. - 0x5 - 0x1 - RW - - - HDPEN - Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. - 0x4 - 0x1 - RW - - - DEVICEEN - Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. - 0x3 - 0x1 - RW - - - NIDEN - Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. - 0x2 - 0x1 - RW - - - DBGEN - Debug enable with signal dbgen. 0: Disabled, 1: Enabled. - 0x1 - 0x1 - RW - - - DFTEN - DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. - 0x0 - 0x1 - RW - - - - - - - - CAN_disable - 0: CAN interface is enabled, 1: CAN interface is disabled. - 0x3 - 0x1 - RW - - - GPU_disable - 0: GPU enabled, 1: GPU disabled. - 0x2 - 0x1 - RW - - - Dual_A7_disable - 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. - 0x1 - 0x1 - RW - - - Crypto_disable - 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. - 0x0 - 0x1 - RW - - - - - - - - W_R conf - This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM - 0x0 - 0x1 - RW - - - - - - - - BSEC_OTP_DISTURBED0 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED1 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED2 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR0 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR1 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR2 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_WRLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK0 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK1 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK2 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK0 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK1 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK2 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - CFG0 - These bits determins the OTP mode encoding - 0x0 - 0x7 - RW - - - - - - - - fdis3 - Disable CAN - 0x3 - 0x1 - RW - - - fdis2 - Disable GPU - 0x2 - 0x1 - RW - - - fdis1 - Disable CPU1 - 0x1 - 0x1 - RW - - - fdis0 - Disable Crypto (license export) - 0x0 - 0x1 - RW - - - - - - - - rma_force - RMA force Bit - 0x0 - 0x1 - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - - - - - - CFG3 - These bits determins the BOOT source definition - 0x0 - 0x20 - RW - - - - - - - - CFG4 - These bits determins the BOOT monotonic counter - 0x0 - 0x20 - RW - - - - - - - - CFG5 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG6 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG7 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG8 - BOOT/Device configuration. - 0x2 - 0x1E - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - rma_lock - RMA lock Bit - 0x0 - 0x1 - RW - - - - - - - - CFG9 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG10 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG11 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG12 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - ID0 - Lot ID on 42bit (11LSB's) - 0x15 - 0xB - RW - - - ID0 - Wafer ID - 0x10 - 0x5 - RW - - - ID0 - Wafer Y coordinates - 0x8 - 0x8 - RW - - - ID0 - Wafer X coordinates - 0x0 - 0x8 - RW - - - - - - - - ID1 - Lot ID on 42bit (31MSB's) - 0x0 - 0x20 - RW - - - - - - - - ID2 - Test program flow T[12],F[12],Q[12] - 0x14 - 0xC - RW - - - ID2 - FT program revision - 0xA - 0xA - RW - - - ID2 - EWS program revision - 0x0 - 0xA - RW - - - - - - - - HW0 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW1 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW2 - Analog TRIM and hardware options - 0x0 - 0x20 - RW - - - - - - - - HW3 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW4 - not used yet - 0x0 - 0x20 - RW - - - - - - - - HW5 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW6 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW7 - reserved - 0x0 - 0x20 - RW - - - - - - - - PKH0 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH1 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH2 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH3 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH4 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH5 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH6 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH7 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - XK0 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK1 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK2 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK3 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK4 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK5 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK6 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK7 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK8 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK9 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK10 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK11 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK12 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK13 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK14 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK15 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK16 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK17 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK18 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK19 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK20 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK21 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK22 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK23 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK24 - RMA lock and relock passwords - 0x0 - 0x20 - RW - - - - - - - - XK25 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK26 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK27 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK28 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK29 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK30 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK31 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK32 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK33 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK34 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK35 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK36 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK37 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK38 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK39 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK40 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK41 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK42 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK43 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK44 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK45 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK46 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK47 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK48 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK49 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK50 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK51 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK52 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK53 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK54 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK55 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK56 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK57 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK58 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK59 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK60 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK61 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK62 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK63 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - ECC_USE - SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. - 0x4 - 0x4 - R - - - SAFMEM_SIZE - SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. - 0x0 - 0x4 - R - - - - - - - - MAJREV - IP Version major revision information. - 0x4 - 0x4 - R - - - MINREV - IP Version minor revision information. - 0x0 - 0x4 - R - - - - - - - - ID - IP Identification. - 0x0 - 0x20 - R - - - - - - - - ID - IP Magic Identification. + version + Structure version 0x0 0x20 R @@ -1815,6 +61,2679 @@ + + Global + + + + + Status + Structure global state + 0x0 + 0x20 + R + + + + + + OTP0 + + + + + Data0 + Data + 0x0 + 0x20 + RW + + + Status0 + Status + 0x4 + 0x20 + R + + + + + + OTP1 + + + + + Data1 + Data + 0x0 + 0x20 + RW + + + Status1 + Status + 0x4 + 0x20 + R + + + RPN + RPN Coding + 0x0 + 0xC + R + + + + + + OTP2 + + + + + Data2 + Data + 0x0 + 0x20 + RW + + + Status2 + Status + 0x4 + 0x20 + R + + + + + + OTP3 + + + + + Data3 + Data + 0x0 + 0x20 + RW + + + Status3 + Status + 0x4 + 0x20 + R + + + qspi_not_default_af + 0:QSPI uses default hard coded AFmux 1:QSPI no default AFmux + 0x0 + 0x1 + RW + + + emmc_if_id + 0:Source is default SDMMC2 1:SDMMC1 2: SDMMC2 + 0x1 + 0x2 + RW + + + sd_if_id + 0:Source is default SDMMC1 1:SDMMC1 2:SDMMC2 + 0x4 + 0x2 + RW + + + no_cpu_pll + 0:PLLs for CPU/AXI are enable 1:PLLs for CPU/AXI are disable + 0x5 + 0x1 + RW + + + no_usb_dp_pullup + 0:USB DP pull-up is set 1: USB DP pull-up is not set + 0x6 + 0x1 + RW + + + uart_instances_disabled + Disable instance 0x1: Reserved 0x2: USART2 0x4: USART3 0x8: USART4 0x10: USART5 0x20: USART6 0x40: USART7 0x80: USART8 + 0x7 + 0x8 + RW + + + no_data_cache + 0:Data cache is used by bootrom 1:Data cache is not used by bootrom + 0xF + 0x1 + RW + + + boot_source_disable + Disable boot source 0x1: FMC 0x2: QSPI NOR 0x4: eMMC 0x8: SD 0x10: UART 0x20: USB 0x40: QSPI NAND + 0x17 + 0x8 + RW + + + second_boot_source + 0:NOT defined 1:FMC NAND 2:QSPI NOR 3:eMMC 4:SD 5:QSPI NAND + 0x18 + 0x3 + RW + + + primary_boot_source + 0:NOT defined 1:FMC NAND 2:QSPI NOR 3:eMMC 4:SD 5:QSPI NAND + 0x1B + 0x3 + RW + + + HSE value + 0: HSE is autodetected 1: 24 MHz 2: 25 MHz 3: 26 MHz + 0x1E + 0x2 + RW + + + + + + OTP4 + + + + + Data4 + Data + 0x0 + 0x20 + RW + + + Status4 + Status + 0x4 + 0x20 + R + + + + + + OTP5 + + + + + Data5 + Data + 0x0 + 0x20 + RW + + + Status5 + Status + 0x4 + 0x20 + R + + + mode0 + + 0x0 + 0x4 + RW + + + afmux0 + AF mux value between 0 and 15 + 0x4 + 0x4 + RW + + + pin0 + pin id between 0 and 15 for GPIOA to GPIOJ and between 0 and 7 for GPIOK and GPIOZ + 0x8 + 0x4 + RW + + + port0 + 0: Unused 1: Bank A 2: Bank B 3: Bank C 4: Bank D 5: Bank E 6: Bank F 7: Bank G 8: Bank H 9: Bank I 10-15: Unused + 0xC + 0x4 + RW + + + mode1 + idem CFG5 mode0 + 0x10 + 0x4 + RW + + + afmux1 + idem CFG5 afmux0 + 0x14 + 0x4 + RW + + + pin1 + idem CFG5 pin0 + 0x18 + 0x4 + RW + + + port1 + idem CFG5 port0 + 0x1C + 0x4 + RW + + + + + + OTP6 + + + + + Data6 + Data + 0x0 + 0x20 + RW + + + Status6 + Status + 0x4 + 0x20 + R + + + mode2 + idem CFG5 port0 + 0x0 + 0x4 + RW + + + afmux2 + idem CFG5 port0 + 0x4 + 0x4 + RW + + + pin2 + idem CFG5 port0 + 0x8 + 0x4 + RW + + + port2 + idem CFG5 port0 + 0xC + 0x4 + RW + + + mode3 + idem CFG5 port0 + 0x10 + 0x4 + RW + + + afmux3 + idem CFG5 port0 + 0x14 + 0x4 + RW + + + pin3 + idem CFG5 port0 + 0x18 + 0x4 + RW + + + port3 + idem CFG5 port0 + 0x1C + 0x4 + RW + + + + + + OTP7 + + + + + Data7 + Data + 0x0 + 0x20 + RW + + + Status7 + Status + 0x4 + 0x20 + R + + + mode4 + idem CFG5 port0 + 0x0 + 0x4 + RW + + + afmux4 + idem CFG5 port0 + 0x4 + 0x4 + RW + + + pin4 + idem CFG5 port0 + 0x8 + 0x4 + RW + + + port4 + idem CFG5 port0 + 0xC + 0x4 + RW + + + mode5 + idem CFG5 port0 + 0x10 + 0x4 + RW + + + afmux5 + idem CFG5 port0 + 0x14 + 0x4 + RW + + + pin5 + idem CFG5 port0 + 0x18 + 0x4 + RW + + + port5 + idem CFG5 port0 + 0x1C + 0x4 + RW + + + + + + OTP8 + + + + + Data8 + Data + 0x0 + 0x20 + RW + + + Status8 + Status + 0x4 + 0x20 + R + + + + + + OTP9 + + + + + Data9 + Data + 0x0 + 0x20 + RW + + + Status9 + Status + 0x4 + 0x20 + R + + + boot_traces_disabled + 0: No 1: Yes + 0x0 + 0x1 + RW + + + hse_frequency_autodetection_disable + 0: No 1: Yes + 0x1 + 0x1 + RW + + + hse_bypass_detection_disable + 0: No 1: Yes + 0x2 + 0x1 + RW + + + emmc_128k_boot_partition + 0: No 1: Yes + 0x4 + 0x1 + RW + + + ssp_req + + 0x5 + 0x1 + RW + + + ssp_success + + 0x6 + 0x1 + RW + + + fsbl_decrypt_prio + 0: Use CRYP 1: Use SAES + 0x7 + 0x1 + RW + + + spinand_need_plane_select + 0:SPI NAND plane select not need 1:SPI NAND plane select is needed + 0xE + 0x1 + RW + + + nand_number_of_ecc_bits + + 0xF + 0x3 + RW + + + nand_bus_width + 0:8 bit 1:16 bit + 0x12 + 0x1 + RW + + + nand_nb_of_blocks + Number of blocks in unit of 256 blocks + 0x13 + 0x8 + RW + + + nand_block_size + 0:64 pages per block 1:128 pages per block 2:256 pages per block + 0x1B + 0x2 + RW + + + nand_page_size + 0:2 Kbytes 1:4 Kbytes 2:8 Kbytes + 0x1D + 0x2 + RW + + + nand_param_stored_in_otp + 0:No 1:Nand parameters bits 15 to 30 are used + 0x1F + 0x1 + RW + + + + + + OTP10 + + + + + Data10 + Data + 0x0 + 0x20 + RW + + + Status10 + Status + 0x4 + 0x20 + R + + + + + + OTP11 + + + + + Data11 + Data + 0x0 + 0x20 + RW + + + Status11 + Status + 0x4 + 0x20 + R + + + + + + OTP12 + + + + + Data12 + Data + 0x0 + 0x20 + RW + + + Status12 + Status + 0x4 + 0x20 + R + + + + + + OTP13 + + + + + Data13 + Data + 0x0 + 0x20 + RW + + + Status13 + Status + 0x4 + 0x20 + R + + + + + + OTP14 + + + + + Data14 + Data + 0x0 + 0x20 + RW + + + Status14 + Status + 0x4 + 0x20 + R + + + + + + OTP15 + + + + + Data15 + Data + 0x0 + 0x20 + RW + + + Status15 + Status + 0x4 + 0x20 + R + + + + + + OTP16 + + + + + Data16 + Data + 0x0 + 0x20 + RW + + + Status16 + Status + 0x4 + 0x20 + R + + + I/O compensation trim + Used for I/O calibration + 0x6 + 0x4 + RW + + + 1V8 reference trim + 1V8 Regulator Trim + 0xC + 0x4 + RW + + + LSI trim + + 0x10 + 0x6 + RW + + + 1V1 reference trim + 1V1 Regulator Trim + 0x16 + 0x5 + RW + + + + + + OTP17 + + + + + Data17 + Data + 0x0 + 0x20 + RW + + + Status17 + Status + 0x4 + 0x20 + R + + + CSITRIM + CSI Trim + 0x0 + 0x8 + RW + + + HSITRIM + HSI Trim + 0x8 + 0xC + RW + + + TEMPHTRIM + High temperature threshold trimming + 0x14 + 0x4 + RW + + + TEMPLTRIM + Low temperature threshold trimming + 0x18 + 0x4 + RW + + + VBATHTRIM + High VBAT threshold trimming + 0x1C + 0x4 + RW + + + + + + OTP18 + + + + + Data18 + Data + 0x0 + 0x20 + RW + + + Status18 + Status + 0x4 + 0x20 + R + + + IWDG1_HW + IWDG1 start 0:Start by software 1:Auto start + 0x3 + 0x1 + RW + + + IWDG2_HW + IWDG2 start 0:Start by software 1:Auto start + 0x4 + 0x1 + RW + + + IWDG1_FZ_STOP + IWDG1 freeze in Stop 0:No 1:Yes + 0x5 + 0x1 + RW + + + IWDG2_FZ_STOP + IWDG2 freeze in Stop 0:No 1:Yes + 0x6 + 0x1 + RW + + + IWDG1_FZ_STANDBY + IWDG1 freeze in Standby 0:No 1:Yes + 0x7 + 0x1 + RW + + + IWDG2_FZ_STANDBY + IWDG2 freeze in Standby 0:No 1:Yes + 0x8 + 0x1 + RW + + + RNG_BYPASS_DISABLE + RNG noise observation 0:Enable 1:Disable + 0x9 + 0x1 + RW + + + SELINBORH + 00: BOR Disabled 01: BOR = 2.1V 10: BOR = 2.4V 11: BOR = 2.7V + 0xB + 0x2 + RW + + + PRODUCT_BELOW_2V5 + Required when VDD is below 2.5 V to allow the SYSCFG high speed lowvoltage enable registers HSLVEN bits to be taken into account. + 0xD + 0x1 + RW + + + + + + OTP19 + + + + + Data19 + Data + 0x0 + 0x20 + RW + + + Status19 + Status + 0x4 + 0x20 + R + + + TS1_FMT0 + DTS frequency measured freq at T0 + 0x0 + 0x10 + RW + + + TS1_RAMP_COEF + DTS ramp coefficient + 0x10 + 0x10 + RW + + + + + + OTP20 + + + + + Data20 + Data + 0x0 + 0x20 + RW + + + Status20 + Status + 0x4 + 0x20 + R + + + TRIM_DTP_R + DTS R Trim + 0x0 + 0x7 + RW + + + TS1_T0 + DTS T0 value + 0x7 + 0x2 + RW + + + VREFINT_CAL + ADC VBG measurement to correct for VREF + 0x10 + 0x10 + RW + + + + + + OTP21 + + + + + Data21 + Data + 0x0 + 0x20 + RW + + + Status21 + Status + 0x4 + 0x20 + R + + + VREFBUFTRIM + 6 trim bits for each of 4 VREFBUF settings + 0x0 + 0x18 + RW + + + SD1COMPCELL + VDDSD1 I/O calibration + 0x18 + 0x4 + RW + + + SD2COMPCELL + VDDSD2 I/O calibration + 0x1c + 0x4 + RW + + + + + + OTP22 + + + + + Data22 + Data + 0x0 + 0x20 + RW + + + Status24 + Status + 0x4 + 0x20 + R + + + + + + OTP23 + + + + + Data23 + Data + 0x0 + 0x20 + RW + + + Status24 + Status + 0x4 + 0x20 + R + + + TS_CAL1 + ADC TEMP measurement at T0 + 0x0 + 0x10 + RW + + + TS_CAL2 + ADC TEMP measurement at T1 + 0x10 + 0x10 + RW + + + + + + OTP24 + + + + + Data24 + Data + 0x0 + 0x20 + RW + + + Status24 + Status + 0x4 + 0x20 + R + + + + + + OTP25 + + + + + Data25 + Data + 0x0 + 0x20 + RW + + + Status25 + Status + 0x4 + 0x20 + R + + + + + + OTP26 + + + + + Data26 + Data + 0x0 + 0x20 + RW + + + Status26 + Status + 0x4 + 0x20 + R + + + + + + OTP27 + + + + + Data27 + Data + 0x0 + 0x20 + RW + + + Status27 + Status + 0x4 + 0x20 + R + + + + + + OTP28 + + + + + Data28 + Data + 0x0 + 0x20 + RW + + + Status28 + Status + 0x4 + 0x20 + R + + + + + + OTP29 + + + + + Data29 + Data + 0x0 + 0x20 + RW + + + Status29 + Status + 0x4 + 0x20 + R + + + + + + OTP30 + + + + + Data30 + Data + 0x0 + 0x20 + RW + + + Status30 + Status + 0x4 + 0x20 + R + + + + + + OTP31 + + + + + Data31 + Data + 0x0 + 0x20 + RW + + + Status31 + Status + 0x4 + 0x20 + R + + + + + + OTP32 + + + + + Data32 + Data + 0x0 + 0x20 + RW + + + Status32 + Status + 0x4 + 0x20 + R + + + + + + OTP33 + + + + + Data33 + Data + 0x0 + 0x20 + RW + + + Status33 + Status + 0x4 + 0x20 + R + + + + + + OTP34 + + + + + Data34 + Data + 0x0 + 0x20 + RW + + + Status34 + Status + 0x4 + 0x20 + R + + + + + + OTP35 + + + + + Data + Data35 + 0x0 + 0x20 + RW + + + Status35 + Status + 0x4 + 0x20 + R + + + + + + OTP36 + + + + + Data36 + Data + 0x0 + 0x20 + RW + + + Status36 + Status + 0x4 + 0x20 + R + + + + + + OTP37 + + + + + Data37 + Data + 0x0 + 0x20 + RW + + + Status37 + Status + 0x4 + 0x20 + R + + + + + + OTP38 + + + + + Data38 + Data + 0x0 + 0x20 + RW + + + Status38 + Status + 0x4 + 0x20 + R + + + + + + OTP39 + + + + + Data39 + Data + 0x0 + 0x20 + RW + + + Status39 + Status + 0x4 + 0x20 + R + + + + + + OTP40 + + + + + Data40 + Data + 0x0 + 0x20 + RW + + + Status40 + Status + 0x4 + 0x20 + R + + + + + + OTP41 + + + + + Data41 + Data + 0x0 + 0x20 + RW + + + Status41 + Status + 0x4 + 0x20 + R + + + + + + OTP42 + + + + + Data42 + Data + 0x0 + 0x20 + RW + + + Status42 + Status + 0x4 + 0x20 + R + + + + + + OTP43 + + + + + Data43 + Data + 0x0 + 0x20 + RW + + + Status43 + Status + 0x4 + 0x20 + R + + + + + + OTP44 + + + + + Data44 + Data + 0x0 + 0x20 + RW + + + Status44 + Status + 0x4 + 0x20 + R + + + + + + OTP45 + + + + + Data45 + Data + 0x0 + 0x20 + RW + + + Status45 + Status + 0x4 + 0x20 + R + + + + + + OTP46 + + + + + Data46 + Data + 0x0 + 0x20 + RW + + + Status46 + Status + 0x4 + 0x20 + R + + + + + + OTP47 + + + + + Data47 + Data + 0x0 + 0x20 + RW + + + Status47 + Status + 0x4 + 0x20 + R + + + + + + OTP48 + + + + + Data48 + Data + 0x0 + 0x20 + RW + + + Status48 + Status + 0x4 + 0x20 + R + + + + + + OTP49 + + + + + Data49 + Data + 0x0 + 0x20 + RW + + + Status49 + Status + 0x4 + 0x20 + R + + + + + + OTP50 + + + + + Data50 + Data + 0x0 + 0x20 + RW + + + Status50 + Status + 0x4 + 0x20 + R + + + + + + OTP51 + + + + + Data51 + Data + 0x0 + 0x20 + RW + + + Status51 + Status + 0x4 + 0x20 + R + + + + + + OTP52 + + + + + Data52 + Data + 0x0 + 0x20 + RW + + + Status52 + Status + 0x4 + 0x20 + R + + + + + + OTP53 + + + + + Data53 + Data + 0x0 + 0x20 + RW + + + Status53 + Status + 0x4 + 0x20 + R + + + + + + OTP54 + + + + + Data54 + Data + 0x0 + 0x20 + RW + + + Status54 + Status + 0x4 + 0x20 + R + + + + + + OTP55 + + + + + Data55 + Data + 0x0 + 0x20 + RW + + + Status55 + Status + 0x4 + 0x20 + R + + + + + + OTP56 + + + + + Data56 + Data + 0x0 + 0x20 + RW + + + Status56 + Status + 0x4 + 0x20 + R + + + + + + OTP57 + + + + + Data57 + Data + 0x0 + 0x20 + RW + + + Status57 + Status + 0x4 + 0x20 + R + + + + + + OTP58 + + + + + Data58 + Data + 0x0 + 0x20 + RW + + + Status58 + Status + 0x4 + 0x20 + R + + + + + + OTP59 + + + + + Data59 + Data + 0x0 + 0x20 + RW + + + Status59 + Status + 0x4 + 0x20 + R + + + + + + OTP60 + + + + + Data60 + Data + 0x0 + 0x20 + RW + + + Status60 + Status + 0x4 + 0x20 + R + + + + + + OTP61 + + + + + Data61 + Data + 0x0 + 0x20 + RW + + + Status61 + Status + 0x4 + 0x20 + R + + + + + + OTP62 + + + + + Data62 + Data + 0x0 + 0x20 + RW + + + Status62 + Status + 0x4 + 0x20 + R + + + + + + OTP63 + + + + + Data63 + Data + 0x0 + 0x20 + RW + + + Status63 + Status + 0x4 + 0x20 + R + + + + + + OTP64 + + + + + Data64 + Data + 0x0 + 0x20 + RW + + + Status64 + Status + 0x4 + 0x20 + R + + + + + + OTP65 + + + + + Data65 + Data + 0x0 + 0x20 + RW + + + Status65 + Status + 0x4 + 0x20 + R + + + + + + OTP66 + + + + + Data66 + Data + 0x0 + 0x20 + RW + + + Status66 + Status + 0x4 + 0x20 + R + + + + + + OTP67 + + + + + Data67 + Data + 0x0 + 0x20 + RW + + + Status67 + Status + 0x4 + 0x20 + R + + + + + + OTP68 + + + + + Data68 + Data + 0x0 + 0x20 + RW + + + Status68 + Status + 0x4 + 0x20 + R + + + + + + OTP69 + + + + + Data69 + Data + 0x0 + 0x20 + RW + + + Status69 + Status + 0x4 + 0x20 + R + + + + + + OTP70 + + + + + Data70 + Data + 0x0 + 0x20 + RW + + + Status70 + Status + 0x4 + 0x20 + R + + + + + + OTP71 + + + + + Data71 + Data + 0x0 + 0x20 + RW + + + Status71 + Status + 0x4 + 0x20 + R + + + + + + OTP72 + + + + + Data72 + Data + 0x0 + 0x20 + RW + + + Status72 + Status + 0x4 + 0x20 + R + + + + + + OTP73 + + + + + Data73 + Data + 0x0 + 0x20 + RW + + + Status73 + Status + 0x4 + 0x20 + R + + + + + + OTP74 + + + + + Data74 + Data + 0x0 + 0x20 + RW + + + Status74 + Status + 0x4 + 0x20 + R + + + + + + OTP75 + + + + + Data75 + Data + 0x0 + 0x20 + RW + + + Status75 + Status + 0x4 + 0x20 + R + + + + + + OTP76 + + + + + Data76 + Data + 0x0 + 0x20 + RW + + + Status76 + Status + 0x4 + 0x20 + R + + + + + + OTP77 + + + + + Data77 + Data + 0x0 + 0x20 + RW + + + Status77 + Status + 0x4 + 0x20 + R + + + + + + OTP78 + + + + + Data78 + Data + 0x0 + 0x20 + RW + + + Status78 + Status + 0x4 + 0x20 + R + + + + + + OTP79 + + + + + Data79 + Data + 0x0 + 0x20 + RW + + + Status79 + Status + 0x4 + 0x20 + R + + + + + + OTP80 + + + + + Data80 + Data + 0x0 + 0x20 + RW + + + Status80 + Status + 0x4 + 0x20 + R + + + + + + OTP81 + + + + + Data81 + Data + 0x0 + 0x20 + RW + + + Status81 + Status + 0x4 + 0x20 + R + + + + + + OTP82 + + + + + Data82 + Data + 0x0 + 0x20 + RW + + + Status82 + Status + 0x4 + 0x20 + R + + + + + + OTP83 + + + + + Data83 + Data + 0x0 + 0x20 + RW + + + Status83 + Status + 0x4 + 0x20 + R + + + + + + OTP84 + + + + + Data84 + Data + 0x0 + 0x20 + RW + + + Status84 + Status + 0x4 + 0x20 + R + + + + + + OTP85 + + + + + Data85 + Data + 0x0 + 0x20 + RW + + + Status85 + Status + 0x4 + 0x20 + R + + + + + + OTP86 + + + + + Data86 + Data + 0x0 + 0x20 + RW + + + Status86 + Status + 0x4 + 0x20 + R + + + + + + OTP87 + + + + + Data87 + Data + 0x0 + 0x20 + RW + + + Status87 + Status + 0x4 + 0x20 + R + + + + + + OTP88 + + + + + Data88 + Data + 0x0 + 0x20 + RW + + + Status88 + Status + 0x4 + 0x20 + R + + + + + + OTP89 + + + + + Data89 + Data + 0x0 + 0x20 + RW + + + Status89 + Status + 0x4 + 0x20 + R + + + + + + OTP90 + + + + + Data90 + Data + 0x0 + 0x20 + RW + + + Status90 + Status + 0x4 + 0x20 + R + + + + + + OTP91 + + + + + Data91 + Data + 0x0 + 0x20 + RW + + + Status91 + Status + 0x4 + 0x20 + R + + + + + + OTP92 + + + + + Data92 + Data + 0x0 + 0x20 + RW + + + Status92 + Status + 0x4 + 0x20 + R + + + + + + OTP93 + + + + + Data93 + Data + 0x0 + 0x20 + RW + + + Status93 + Status + 0x4 + 0x20 + R + + + + + + OTP94 + + + + + Data94 + Data + 0x0 + 0x20 + RW + + + Status94 + Status + 0x4 + 0x20 + R + + + + + + OTP95 + + + + + Data95 + Data + 0x0 + 0x20 + RW + + + Status95 + Status + 0x4 + 0x20 + R + + + + diff --git a/misc/install/STM32_Programmer_CLI/bin/JLink_x64.dll b/misc/install/STM32_Programmer_CLI/bin/JLink_x64.dll new file mode 100644 index 0000000000..0823744b82 Binary files /dev/null and b/misc/install/STM32_Programmer_CLI/bin/JLink_x64.dll differ diff --git a/misc/install/STM32_Programmer_CLI/bin/Qt5Core.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5Core.dll deleted file mode 100644 index 5d1c167c7e..0000000000 Binary files a/misc/install/STM32_Programmer_CLI/bin/Qt5Core.dll and /dev/null differ diff --git a/misc/install/STM32_Programmer_CLI/bin/Qt5Script.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5Script.dll deleted file mode 100644 index 315b5cf3af..0000000000 Binary files a/misc/install/STM32_Programmer_CLI/bin/Qt5Script.dll and /dev/null differ diff --git a/misc/install/STM32_Programmer_CLI/bin/Qt5SerialPort.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5SerialPort.dll deleted file mode 100644 index 22893bf285..0000000000 Binary files a/misc/install/STM32_Programmer_CLI/bin/Qt5SerialPort.dll and /dev/null differ diff --git a/misc/install/STM32_Programmer_CLI/bin/Qt5Xml.dll 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